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GICH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

HCR

MISR

LR0

LR1

LR2

LR3

EISR0

ELSR0

VTR

VMCR

APR0


HCR

GICH hypervisor control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCR HCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN UIE LRENPIE NPIE VGRP0EIE VGRP0DIE VGRP1EIE VGRP1DIE EOICOUNT

EN : global enable bit for the virtual CPU interface
bits : 0 - 0 (1 bit)

UIE : underflow interrupt enable
bits : 1 - 1 (1 bit)

LRENPIE : list register entry not present interrupt enable
bits : 2 - 2 (1 bit)

NPIE : no pending interrupt enable
bits : 3 - 3 (1 bit)

VGRP0EIE : virtual machine enable group 0interrupt enable
bits : 4 - 4 (1 bit)

VGRP0DIE : virtual machine disable group 0interrupt enable
bits : 5 - 5 (1 bit)

VGRP1EIE : virtual machine enable group 1 interrupt enable
bits : 6 - 6 (1 bit)

VGRP1DIE : virtual machine disable group 1 interrupt enable
bits : 7 - 7 (1 bit)

EOICOUNT : end-of-interrupt counter
bits : 27 - 31 (5 bit)


MISR

GICH maintenance interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MISR MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOI U LRENP NP VGRP0E VGRP0D VGRP1E VGRP1D

EOI : End of interrupt maintenance interrupt
bits : 0 - 0 (1 bit)

U : underflow maintenance interrupt
bits : 1 - 1 (1 bit)

LRENP : list register entry not present maintenance interrupt
bits : 2 - 2 (1 bit)

NP : no pending maintenance interrupt
bits : 3 - 3 (1 bit)

VGRP0E : enabled group 0 maintenance interrupt
bits : 4 - 4 (1 bit)

VGRP0D : disabled group 0 maintenance interrupt
bits : 5 - 5 (1 bit)

VGRP1E : enabled group 1 maintenance interrupt
bits : 6 - 6 (1 bit)

VGRP1D : disabled group 1 maintenance interrupt
bits : 7 - 7 (1 bit)


LR0

GICH list register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LR0 LR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIRTUALID PHYSICALID PRIORITY STATE GRP1 HW

VIRTUALID : virtual ID
bits : 0 - 9 (10 bit)

PHYSICALID : physical ID
bits : 10 - 19 (10 bit)

PRIORITY : priority of the interrupt
bits : 23 - 27 (5 bit)

STATE : state of the interrupt
bits : 28 - 29 (2 bit)

GRP1 : Indicates whether this virtual interrupt is a group 1 virtual interrupt
bits : 30 - 30 (1 bit)

HW : hardware interrupt
bits : 31 - 31 (1 bit)


LR1

GICH list register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LR1 LR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIRTUALID PHYSICALID PRIORITY STATE GRP1 HW

VIRTUALID : virtual ID
bits : 0 - 9 (10 bit)

PHYSICALID : physical ID
bits : 10 - 19 (10 bit)

PRIORITY : priority of the interrupt
bits : 23 - 27 (5 bit)

STATE : state of the interrupt
bits : 28 - 29 (2 bit)

GRP1 : Indicates whether this virtual interrupt is a group 1 virtual interrupt
bits : 30 - 30 (1 bit)

HW : hardware interrupt
bits : 31 - 31 (1 bit)


LR2

GICH list register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LR2 LR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIRTUALID PHYSICALID PRIORITY STATE GRP1 HW

VIRTUALID : virtual ID
bits : 0 - 9 (10 bit)

PHYSICALID : physical ID
bits : 10 - 19 (10 bit)

PRIORITY : priority of the interrupt
bits : 23 - 27 (5 bit)

STATE : state of the interrupt
bits : 28 - 29 (2 bit)

GRP1 : Indicates whether this virtual interrupt is a group 1 virtual interrupt
bits : 30 - 30 (1 bit)

HW : hardware interrupt
bits : 31 - 31 (1 bit)


LR3

GICH list register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LR3 LR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIRTUALID PHYSICALID PRIORITY STATE GRP1 HW

VIRTUALID : virtual ID
bits : 0 - 9 (10 bit)

PHYSICALID : physical ID
bits : 10 - 19 (10 bit)

PRIORITY : priority of the interrupt
bits : 23 - 27 (5 bit)

STATE : state of the interrupt
bits : 28 - 29 (2 bit)

GRP1 : Indicates whether this virtual interrupt is a group 1 virtual interrupt
bits : 30 - 30 (1 bit)

HW : hardware interrupt
bits : 31 - 31 (1 bit)


EISR0

GICH end of interrupt status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EISR0 EISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EISR0

EISR0 : end of interrupt status
bits : 0 - 31 (32 bit)


ELSR0

GICH empty list status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ELSR0 ELSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELSR0

ELSR0 : end of interrupt status
bits : 0 - 31 (32 bit)


VTR

GICH VGIC type register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VTR VTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LISTREGS PREBITS PRIBITS

LISTREGS : list registers
bits : 0 - 4 (5 bit)

PREBITS : preemption bits
bits : 26 - 28 (3 bit)

PRIBITS : priority bits
bits : 29 - 31 (3 bit)


VMCR

GICH virtual machine control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VMCR VMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMGRP0EN VMGRP1EN VMACKCTL VMFIQEN VMCBPR VEM VMABP VMBP VMPRIMASK

VMGRP0EN : alias of GICV_CTLR.ENABLEGRP0
bits : 0 - 0 (1 bit)

VMGRP1EN : alias of GICV_CTLR.ENABLEGRP1
bits : 1 - 1 (1 bit)

VMACKCTL : alias of GICV_CTLR.ACKCTL
bits : 2 - 2 (1 bit)

VMFIQEN : alias of GICV_CTLR.FIQEN
bits : 3 - 3 (1 bit)

VMCBPR : alias of GICV_CTLR.CBPR
bits : 4 - 4 (1 bit)

VEM : alias of GICV_CTLR.EOIMODE
bits : 9 - 9 (1 bit)

VMABP : alias of GICV_ABPR.BINARY_POINT
bits : 18 - 20 (3 bit)

VMBP : alias of GICV_BPR.BINARY_POINT
bits : 21 - 23 (3 bit)

VMPRIMASK : alias of GICV_PMR.PRIORITY
bits : 27 - 31 (5 bit)


APR0

GICH active priority register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

APR0 APR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APR0

APR0 : active priority
bits : 0 - 31 (32 bit)



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