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GICC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTLR

CTLRNS

EOIR

DIR

RPR

HPPIR

ABPR

AIAR

AEOIR

AHPPIR

PMR

BPR

BPRNS

IAR

APR0

NSAPR0

IIDR


CTLR

Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLEGRP0 ENABLEGRP1 ACKCTL FIQEN CBPR FIQBYPDISGRP0 IRQBYPDISGRP0 FIQBYPDISGRP1 IRQBYPDISGRP1 EOIMODES EOIMODENS

ENABLEGRP0 : Enable group 0 interrupts
bits : 0 - 0 (1 bit)

ENABLEGRP1 : Enable group 1 interrupts
bits : 1 - 1 (1 bit)

ACKCTL : Acknowledge control
bits : 2 - 2 (1 bit)

FIQEN : FIQ enable for group 0 interrupts
bits : 3 - 3 (1 bit)

CBPR : BPR control
bits : 4 - 4 (1 bit)

FIQBYPDISGRP0 : FIQ bypass disable for group 0 interrupts
bits : 5 - 5 (1 bit)

IRQBYPDISGRP0 : IRQ bypass disable for group 0 interrupts
bits : 6 - 6 (1 bit)

FIQBYPDISGRP1 : Alias of FIQBYPDISGRP1 from the non-secure copy of this register.
bits : 7 - 7 (1 bit)

IRQBYPDISGRP1 : Alias of IRQBYPDISGRP1 from the non-secure copy of this register
bits : 8 - 8 (1 bit)

EOIMODES : EOI mode for secure accesses
bits : 9 - 9 (1 bit)

EOIMODENS : Alias of EOIMODENS from the non-secure copy of this register
bits : 10 - 10 (1 bit)


CTLRNS

GICC control (non-secure access) register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTLR
reset_Mask : 0x0

CTLRNS CTLRNS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLEGRP1 FIQBYPDISGRP1 IRQBYPDISGRP1 EOIMODENS

ENABLEGRP1 : Enable group1 interrupts
bits : 0 - 0 (1 bit)

FIQBYPDISGRP1 : FIQ bypass disable for group 1 interrupts
bits : 5 - 5 (1 bit)

IRQBYPDISGRP1 : IRQ bypass for group 1 interrupts
bits : 6 - 6 (1 bit)

EOIMODENS : EOI mode for non- secure accesses
bits : 9 - 9 (1 bit)


EOIR

GICC end of interrupt register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EOIR EOIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOIINTID CPUID

EOIINTID : EOIINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


DIR

GICC deactivate interrupt register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIR DIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


RPR

GICC running priority register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RPR RPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY

PRIORITY : current running priority on the CPU interface
bits : 3 - 7 (5 bit)


HPPIR

GICC highest priority pending interrupt register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HPPIR HPPIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDINTID CPUID

PENDINTID : PENDINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


ABPR

GICC aliased binary point register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABPR ABPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY_POINT

BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)


AIAR

GICC aliased interrupt acknowledge register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AIAR AIAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


AEOIR

GICC aliased end of interrupt register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AEOIR AEOIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOIINTID CPUID

EOIINTID : EOIINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


AHPPIR

GICC aliased highest priority pending interrupt register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AHPPIR AHPPIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDINTID CPUID

PENDINTID : PENDINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


PMR

GICC input priority mask register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMR PMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY

PRIORITY : priority mask level for the CPU interface
bits : 3 - 7 (5 bit)


BPR

GICC binary point register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BPR BPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY_POINT

BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)


BPRNS

GICC binary point (non-secure access) register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : BPR
reset_Mask : 0x0

BPRNS BPRNS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY_POINT

BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)


IAR

GICC interrupt acknowledge register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IAR IAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : The interrupt ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


APR0

GICC active priority register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APR0 APR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APR0

APR0 : APR0
bits : 0 - 31 (32 bit)


NSAPR0

GICC non-secure active priority register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSAPR0 NSAPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAPR0

NSAPR0 : NSAPR0
bits : 0 - 31 (32 bit)


IIDR

GICC interface identification register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IIDR IIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMPLEMENTER REVISION ARCH PRODUCTID

IMPLEMENTER : IMPLEMENTER
bits : 0 - 11 (12 bit)

REVISION : REVISION
bits : 12 - 15 (4 bit)

ARCH : ARCH
bits : 16 - 19 (4 bit)

PRODUCTID : PRODUCTID
bits : 20 - 31 (12 bit)



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