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LTDC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

LTDC_IDR (IDR)

LTDC_AWCR (AWCR)

LTDC_L2CR (L2CR)

LTDC_L2WHPCR (L2WHPCR)

LTDC_L2WVPCR (L2WVPCR)

LTDC_L2CKCR (L2CKCR)

LTDC_L2PFCR (L2PFCR)

LTDC_L2CACR (L2CACR)

LTDC_L2DCCR (L2DCCR)

LTDC_L2BFCR (L2BFCR)

LTDC_L2CFBAR (L2CFBAR)

LTDC_L2CFBLR (L2CFBLR)

LTDC_L2CFBLNR (L2CFBLNR)

LTDC_TWCR (TWCR)

LTDC_L2CLUTWR (L2CLUTWR)

LTDC_GCR (GCR)

LTDC_GC1R (GC1R)

LTDC_GC2R (GC2R)

LTDC_SRCR (SRCR)

LTDC_BCCR (BCCR)

LTDC_IER (IER)

LTDC_ISR (ISR)

LTDC_ICR (ICR)

LTDC_LCR (LCR)

LTDC_LIPCR (LIPCR)

LTDC_CPSR (CPSR)

LTDC_CDSR (CDSR)

LTDC_SSCR (SSCR)

LTDC_L1CR (L1CR)

LTDC_L1WHPCR (L1WHPCR)

LTDC_L1WVPCR (L1WVPCR)

LTDC_L1CKCR (L1CKCR)

LTDC_L1PFCR (L1PFCR)

LTDC_L1CACR (L1CACR)

LTDC_L1DCCR (L1DCCR)

LTDC_L1BFCR (L1BFCR)

LTDC_L1CFBAR (L1CFBAR)

LTDC_L1CFBLR (L1CFBLR)

LTDC_L1CFBLNR (L1CFBLNR)

LTDC_BPCR (BPCR)

LTDC_L1CLUTWR (L1CLUTWR)


LTDC_IDR (IDR)

LTDC identification register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_IDR LTDC_IDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV MINVER MAJVER

REV : REV
bits : 0 - 7 (8 bit)
access : read-only

MINVER : MINVER
bits : 8 - 15 (8 bit)
access : read-only

MAJVER : MAJVER
bits : 16 - 23 (8 bit)
access : read-only


LTDC_AWCR (AWCR)

This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure120 and Section19.4: LTDC programmable parameters for an example of configuration.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_AWCR LTDC_AWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AAH AAW

AAH : AAH
bits : 0 - 11 (12 bit)
access : read-write

AAW : AAW
bits : 16 - 27 (12 bit)
access : read-write


LTDC_L2CR (L2CR)

LTDC layer 2 control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2CR LTDC_L2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN COLKEN CLUTEN

LEN : LEN
bits : 0 - 0 (1 bit)
access : read-write

COLKEN : COLKEN
bits : 1 - 1 (1 bit)
access : read-write

CLUTEN : CLUTEN
bits : 4 - 4 (1 bit)
access : read-write


LTDC_L2WHPCR (L2WHPCR)

This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[10:0] bits in the LTDC_AWCR register.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2WHPCR LTDC_L2WHPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WHSTPOS WHSPPOS

WHSTPOS : WHSTPOS
bits : 0 - 11 (12 bit)
access : read-write

WHSPPOS : WHSPPOS
bits : 16 - 27 (12 bit)
access : read-write


LTDC_L2WVPCR (L2WVPCR)

This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2WVPCR LTDC_L2WVPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WVSTPOS WVSPPOS

WVSTPOS : WVSTPOS
bits : 0 - 11 (12 bit)
access : read-write

WVSPPOS : WVSPPOS
bits : 16 - 27 (12 bit)
access : read-write


LTDC_L2CKCR (L2CKCR)

This register defines the color key value (RGB), that is used by the color keying.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2CKCR LTDC_L2CKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKBLUE CKGREEN CKRED

CKBLUE : CKBLUE
bits : 0 - 7 (8 bit)
access : read-write

CKGREEN : CKGREEN
bits : 8 - 15 (8 bit)
access : read-write

CKRED : CKRED
bits : 16 - 23 (8 bit)
access : read-write


LTDC_L2PFCR (L2PFCR)

This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2PFCR LTDC_L2PFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF

PF : PF
bits : 0 - 2 (3 bit)
access : read-write


LTDC_L2CACR (L2CACR)

This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2CACR LTDC_L2CACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONSTA

CONSTA : CONSTA
bits : 0 - 7 (8 bit)
access : read-write


LTDC_L2DCCR (L2DCCR)

This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2DCCR LTDC_L2DCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCBLUE DCGREEN DCRED DCALPHA

DCBLUE : DCBLUE
bits : 0 - 7 (8 bit)
access : read-write

DCGREEN : DCGREEN
bits : 8 - 15 (8 bit)
access : read-write

DCRED : DCRED
bits : 16 - 23 (8 bit)
access : read-write

DCALPHA : DCALPHA
bits : 24 - 31 (8 bit)
access : read-write


LTDC_L2BFCR (L2BFCR)

This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2BFCR LTDC_L2BFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BF2 BF1

BF2 : BF2
bits : 0 - 2 (3 bit)
access : read-write

BF1 : BF1
bits : 8 - 10 (3 bit)
access : read-write


LTDC_L2CFBAR (L2CFBAR)

This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2CFBAR LTDC_L2CFBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBADD

CFBADD : CFBADD
bits : 0 - 31 (32 bit)
access : read-write


LTDC_L2CFBLR (L2CFBLR)

This register defines the color frame buffer line length and pitch.
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2CFBLR LTDC_L2CFBLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLL CFBP

CFBLL : CFBLL
bits : 0 - 13 (14 bit)
access : read-write

CFBP : CFBP
bits : 16 - 29 (14 bit)
access : read-write


LTDC_L2CFBLNR (L2CFBLNR)

This register defines the number of lines in the color frame buffer.
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2CFBLNR LTDC_L2CFBLNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLNBR

CFBLNBR : CFBLNBR
bits : 0 - 11 (12 bit)
access : read-write


LTDC_TWCR (TWCR)

This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure120 and Section19.4: LTDC programmable parameters for an example of configuration.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_TWCR LTDC_TWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOTALH TOTALW

TOTALH : TOTALH
bits : 0 - 11 (12 bit)
access : read-write

TOTALW : TOTALW
bits : 16 - 27 (12 bit)
access : read-write


LTDC_L2CLUTWR (L2CLUTWR)

This register defines the CLUT address and the RGB value.
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_L2CLUTWR LTDC_L2CLUTWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED CLUTADD

BLUE : BLUE
bits : 0 - 7 (8 bit)
access : write-only

GREEN : GREEN
bits : 8 - 15 (8 bit)
access : write-only

RED : RED
bits : 16 - 23 (8 bit)
access : write-only

CLUTADD : CLUTADD
bits : 24 - 31 (8 bit)
access : write-only


LTDC_GCR (GCR)

This register defines the global configuration of the LCD-TFT controller.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_GCR LTDC_GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDCEN DBW DGW DRW DEN PCPOL DEPOL VSPOL HSPOL

LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
access : read-write

DBW : DBW
bits : 4 - 6 (3 bit)
access : read-only

DGW : DGW
bits : 8 - 10 (3 bit)
access : read-only

DRW : DRW
bits : 12 - 14 (3 bit)
access : read-only

DEN : DEN
bits : 16 - 16 (1 bit)
access : read-write

PCPOL : PCPOL
bits : 28 - 28 (1 bit)
access : read-write

DEPOL : DEPOL
bits : 29 - 29 (1 bit)
access : read-write

VSPOL : VSPOL
bits : 30 - 30 (1 bit)
access : read-write

HSPOL : HSPOL
bits : 31 - 31 (1 bit)
access : read-write


LTDC_GC1R (GC1R)

LTDC global configuration 1 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_GC1R LTDC_GC1R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WBCH WGCH WRCH PRBEN DT GCT SHREN BCP BBEN LNIP TP IPP SPP DWP STREN BMEN

WBCH : WBCH
bits : 0 - 3 (4 bit)
access : read-only

WGCH : WGCH
bits : 4 - 7 (4 bit)
access : read-only

WRCH : WRCH
bits : 8 - 11 (4 bit)
access : read-only

PRBEN : PRBEN
bits : 12 - 12 (1 bit)
access : read-only

DT : DT
bits : 14 - 15 (2 bit)
access : read-only

GCT : GCT
bits : 17 - 19 (3 bit)
access : read-only

SHREN : SHREN
bits : 21 - 21 (1 bit)
access : read-only

BCP : BCP
bits : 22 - 22 (1 bit)
access : read-only

BBEN : BBEN
bits : 23 - 23 (1 bit)
access : read-only

LNIP : LNIP
bits : 24 - 24 (1 bit)
access : read-only

TP : TP
bits : 25 - 25 (1 bit)
access : read-only

IPP : IPP
bits : 26 - 26 (1 bit)
access : read-only

SPP : SPP
bits : 27 - 27 (1 bit)
access : read-only

DWP : DWP
bits : 28 - 28 (1 bit)
access : read-only

STREN : STREN
bits : 29 - 29 (1 bit)
access : read-only

BMEN : BMEN
bits : 31 - 31 (1 bit)
access : read-only


LTDC_GC2R (GC2R)

LTDC global configuration 2 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_GC2R LTDC_GC2R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EDCEN STSAEN DVAEN DPAEN BW EDCA

EDCEN : EDCEN
bits : 0 - 0 (1 bit)
access : read-only

STSAEN : STSAEN
bits : 1 - 1 (1 bit)
access : read-only

DVAEN : DVAEN
bits : 2 - 2 (1 bit)
access : read-only

DPAEN : DPAEN
bits : 3 - 3 (1 bit)
access : read-only

BW : BW
bits : 4 - 6 (3 bit)
access : read-only

EDCA : EDCA
bits : 7 - 7 (1 bit)
access : read-only


LTDC_SRCR (SRCR)

This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_SRCR LTDC_SRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR VBR

IMR : IMR
bits : 0 - 0 (1 bit)
access : read-write

VBR : VBR
bits : 1 - 1 (1 bit)
access : read-write


LTDC_BCCR (BCCR)

This register defines the background color (RGB888).
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_BCCR LTDC_BCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCBLUE BCGREEN BCRED

BCBLUE : BCBLUE
bits : 0 - 7 (8 bit)
access : read-write

BCGREEN : BCGREEN
bits : 8 - 15 (8 bit)
access : read-write

BCRED : BCRED
bits : 16 - 23 (8 bit)
access : read-write


LTDC_IER (IER)

This register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_IER LTDC_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIE FUIE TERRIE RRIE

LIE : LIE
bits : 0 - 0 (1 bit)
access : read-write

FUIE : FUIE
bits : 1 - 1 (1 bit)
access : read-write

TERRIE : TERRIE
bits : 2 - 2 (1 bit)
access : read-write

RRIE : RRIE
bits : 3 - 3 (1 bit)
access : read-write


LTDC_ISR (ISR)

This register returns the interrupt status flag.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_ISR LTDC_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIF FUIF TERRIF RRIF

LIF : LIF
bits : 0 - 0 (1 bit)
access : read-only

FUIF : FUIF
bits : 1 - 1 (1 bit)
access : read-only

TERRIF : TERRIF
bits : 2 - 2 (1 bit)
access : read-only

RRIF : RRIF
bits : 3 - 3 (1 bit)
access : read-only


LTDC_ICR (ICR)

LTDC Interrupt Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_ICR LTDC_ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLIF CFUIF CTERRIF CRRIF

CLIF : CLIF
bits : 0 - 0 (1 bit)
access : write-only

CFUIF : CFUIF
bits : 1 - 1 (1 bit)
access : write-only

CTERRIF : CTERRIF
bits : 2 - 2 (1 bit)
access : write-only

CRRIF : CRRIF
bits : 3 - 3 (1 bit)
access : write-only


LTDC_LCR (LCR)

LDTC layer count register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_LCR LTDC_LCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNBR

LNBR : LNBR
bits : 0 - 7 (8 bit)
access : read-only


LTDC_LIPCR (LIPCR)

This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure120.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_LIPCR LTDC_LIPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIPOS

LIPOS : LIPOS
bits : 0 - 11 (12 bit)
access : read-write


LTDC_CPSR (CPSR)

LTDC current position status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_CPSR LTDC_CPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CYPOS CXPOS

CYPOS : CYPOS
bits : 0 - 15 (16 bit)
access : read-only

CXPOS : CXPOS
bits : 16 - 31 (16 bit)
access : read-only


LTDC_CDSR (CDSR)

This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_CDSR LTDC_CDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDES HDES VSYNCS HSYNCS

VDES : VDES
bits : 0 - 0 (1 bit)
access : read-only

HDES : HDES
bits : 1 - 1 (1 bit)
access : read-only

VSYNCS : VSYNCS
bits : 2 - 2 (1 bit)
access : read-only

HSYNCS : HSYNCS
bits : 3 - 3 (1 bit)
access : read-only


LTDC_SSCR (SSCR)

This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure120 and Section19.4: LTDC programmable parameters for an example of configuration.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_SSCR LTDC_SSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSH HSW

VSH : VSH
bits : 0 - 11 (12 bit)
access : read-write

HSW : HSW
bits : 16 - 27 (12 bit)
access : read-write


LTDC_L1CR (L1CR)

LTDC layer 1 control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1CR LTDC_L1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN COLKEN CLUTEN

LEN : LEN
bits : 0 - 0 (1 bit)
access : read-write

COLKEN : COLKEN
bits : 1 - 1 (1 bit)
access : read-write

CLUTEN : CLUTEN
bits : 4 - 4 (1 bit)
access : read-write


LTDC_L1WHPCR (L1WHPCR)

This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[10:0] bits in the LTDC_AWCR register.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1WHPCR LTDC_L1WHPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WHSTPOS WHSPPOS

WHSTPOS : WHSTPOS
bits : 0 - 11 (12 bit)
access : read-write

WHSPPOS : WHSPPOS
bits : 16 - 27 (12 bit)
access : read-write


LTDC_L1WVPCR (L1WVPCR)

This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1WVPCR LTDC_L1WVPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WVSTPOS WVSPPOS

WVSTPOS : WVSTPOS
bits : 0 - 11 (12 bit)
access : read-write

WVSPPOS : WVSPPOS
bits : 16 - 27 (12 bit)
access : read-write


LTDC_L1CKCR (L1CKCR)

This register defines the color key value (RGB), that is used by the color keying.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1CKCR LTDC_L1CKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKBLUE CKGREEN CKRED

CKBLUE : CKBLUE
bits : 0 - 7 (8 bit)
access : read-write

CKGREEN : CKGREEN
bits : 8 - 15 (8 bit)
access : read-write

CKRED : CKRED
bits : 16 - 23 (8 bit)
access : read-write


LTDC_L1PFCR (L1PFCR)

This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1PFCR LTDC_L1PFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF

PF : PF
bits : 0 - 2 (3 bit)
access : read-write


LTDC_L1CACR (L1CACR)

This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1CACR LTDC_L1CACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONSTA

CONSTA : CONSTA
bits : 0 - 7 (8 bit)
access : read-write


LTDC_L1DCCR (L1DCCR)

This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1DCCR LTDC_L1DCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCBLUE DCGREEN DCRED DCALPHA

DCBLUE : DCBLUE
bits : 0 - 7 (8 bit)
access : read-write

DCGREEN : DCGREEN
bits : 8 - 15 (8 bit)
access : read-write

DCRED : DCRED
bits : 16 - 23 (8 bit)
access : read-write

DCALPHA : DCALPHA
bits : 24 - 31 (8 bit)
access : read-write


LTDC_L1BFCR (L1BFCR)

This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1BFCR LTDC_L1BFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BF2 BF1

BF2 : BF2
bits : 0 - 2 (3 bit)
access : read-write

BF1 : BF1
bits : 8 - 10 (3 bit)
access : read-write


LTDC_L1CFBAR (L1CFBAR)

This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1CFBAR LTDC_L1CFBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBADD

CFBADD : CFBADD
bits : 0 - 31 (32 bit)
access : read-write


LTDC_L1CFBLR (L1CFBLR)

This register defines the color frame buffer line length and pitch.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1CFBLR LTDC_L1CFBLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLL CFBP

CFBLL : CFBLL
bits : 0 - 13 (14 bit)
access : read-write

CFBP : CFBP
bits : 16 - 29 (14 bit)
access : read-write


LTDC_L1CFBLNR (L1CFBLNR)

This register defines the number of lines in the color frame buffer.
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1CFBLNR LTDC_L1CFBLNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLNBR

CFBLNBR : CFBLNBR
bits : 0 - 11 (12 bit)
access : read-write


LTDC_BPCR (BPCR)

This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure120 and Section19.4: LTDC programmable parameters for an example of configuration.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTDC_BPCR LTDC_BPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVBP AHBP

AVBP : AVBP
bits : 0 - 11 (12 bit)
access : read-write

AHBP : AHBP
bits : 16 - 27 (12 bit)
access : read-write


LTDC_L1CLUTWR (L1CLUTWR)

This register defines the CLUT address and the RGB value.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LTDC_L1CLUTWR LTDC_L1CLUTWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED CLUTADD

BLUE : BLUE
bits : 0 - 7 (8 bit)
access : write-only

GREEN : GREEN
bits : 8 - 15 (8 bit)
access : write-only

RED : RED
bits : 16 - 23 (8 bit)
access : write-only

CLUTADD : CLUTADD
bits : 24 - 31 (8 bit)
access : write-only



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