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DSI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DSI_VR (VR)

DSI_LCOLCR (LCOLCR)

DSI_VSCR (VSCR)

DSI_LCVCIDR (LCVCIDR)

DSI_LCCCR (LCCCR)

DSI_LPMCCR (LPMCCR)

DSI_VMCCR (VMCCR)

DSI_VPCCR (VPCCR)

DSI_LPCR (LPCR)

DSI_VCCCR (VCCCR)

DSI_VNPCCR (VNPCCR)

DSI_VHSACCR (VHSACCR)

DSI_VHBPCCR (VHBPCCR)

DSI_VLCCR (VLCCR)

DSI_VVSACCR (VVSACCR)

DSI_VVBPCCR (VVBPCCR)

DSI_VVFPCCR (VVFPCCR)

DSI_VVACCR (VVACCR)

DSI_LPMCR (LPMCR)

DSI_PCR (PCR)

DSI_GVCIDR (GVCIDR)

DSI_MCR (MCR)

DSI_VMCR (VMCR)

DSI_VPCR (VPCR)

DSI_CR (CR)

DSI_VCCR (VCCR)

DSI_WCFGR (WCFGR)

DSI_WCR (WCR)

DSI_WIER (WIER)

DSI_WISR (WISR)

DSI_WIFCR (WIFCR)

DSI_WPCR0 (WPCR0)

DSI_WPCR1 (WPCR1)

DSI_WRPCR (WRPCR)

DSI_VNPCR (VNPCR)

DSI_VHSACR (VHSACR)

DSI_VHBPCR (VHBPCR)

DSI_VLCR (VLCR)

DSI_VVSACR (VVSACR)

DSI_VVBPCR (VVBPCR)

DSI_VVFPCR (VVFPCR)

DSI_VVACR (VVACR)

DSI_LCCR (LCCR)

DSI_CMCR (CMCR)

DSI_GHCR (GHCR)

DSI_GPDR (GPDR)

DSI_GPSR (GPSR)

DSI_TCCR0 (TCCR0)

DSI_TCCR1 (TCCR1)

DSI_HWCFGR (HWCFGR)

DSI_VERR (VERR)

DSI_IPIDR (IPIDR)

DSI_SIDR (SIDR)

DSI_CCR (CCR)

DSI_TCCR2 (TCCR2)

DSI_TCCR3 (TCCR3)

DSI_TCCR4 (TCCR4)

DSI_TCCR5 (TCCR5)

DSI_CLCR (CLCR)

DSI_CLTCR (CLTCR)

DSI_DLTCR (DLTCR)

DSI_PCTLR (PCTLR)

DSI_PCONFR (PCONFR)

DSI_PUCR (PUCR)

DSI_PTTCR (PTTCR)

DSI_PSR (PSR)

DSI_ISR0 (ISR0)

DSI_LVCIDR (LVCIDR)

DSI_ISR1 (ISR1)

DSI_IER0 (IER0)

DSI_IER1 (IER1)

DSI_FIR0 (FIR0)

DSI_FIR1 (FIR1)

DSI_DLTRCR (DLTRCR)


DSI_VR (VR)

DSI Host version register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VR DSI_VR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION

VERSION : VERSION
bits : 0 - 31 (32 bit)
access : read-only


DSI_LCOLCR (LCOLCR)

DSI Host LTDC color coding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LCOLCR DSI_LCOLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLC LPE

COLC : COLC
bits : 0 - 3 (4 bit)
access : read-write

LPE : LPE
bits : 8 - 8 (1 bit)
access : read-write


DSI_VSCR (VSCR)

DSI Host video shadow control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VSCR DSI_VSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN UR

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

UR : UR
bits : 8 - 8 (1 bit)
access : read-write


DSI_LCVCIDR (LCVCIDR)

DSI Host LTDC current VCID register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LCVCIDR DSI_LCVCIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : VCID
bits : 0 - 1 (2 bit)
access : read-write


DSI_LCCCR (LCCCR)

DSI Host LTDC current color coding register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_LCCCR DSI_LCCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLC LPE

COLC : COLC
bits : 0 - 3 (4 bit)
access : read-only

LPE : LPE
bits : 8 - 8 (1 bit)
access : read-only


DSI_LPMCCR (LPMCCR)

DSI Host low-power mode current configuration register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_LPMCCR DSI_LPMCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLPSIZE LPSIZE

VLPSIZE : VLPSIZE
bits : 0 - 7 (8 bit)
access : read-only

LPSIZE : LPSIZE
bits : 16 - 23 (8 bit)
access : read-only


DSI_VMCCR (VMCCR)

DSI Host video mode current configuration register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VMCCR DSI_VMCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMT LPVSAE LPVBPE LPVFPE LPVAE LPHBPE LPHFE FBTAAE LPCE

VMT : VMT
bits : 0 - 1 (2 bit)
access : read-only

LPVSAE : LPVSAE
bits : 2 - 2 (1 bit)
access : read-only

LPVBPE : LPVBPE
bits : 3 - 3 (1 bit)
access : read-only

LPVFPE : LPVFPE
bits : 4 - 4 (1 bit)
access : read-only

LPVAE : LPVAE
bits : 5 - 5 (1 bit)
access : read-only

LPHBPE : LPHBPE
bits : 6 - 6 (1 bit)
access : read-only

LPHFE : LPHFE
bits : 7 - 7 (1 bit)
access : read-only

FBTAAE : FBTAAE
bits : 8 - 8 (1 bit)
access : read-only

LPCE : LPCE
bits : 9 - 9 (1 bit)
access : read-only


DSI_VPCCR (VPCCR)

DSI Host video packet current configuration register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VPCCR DSI_VPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPSIZE

VPSIZE : VPSIZE
bits : 0 - 13 (14 bit)
access : read-only


DSI_LPCR (LPCR)

DSI Host LTDC polarity configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LPCR DSI_LPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEP VSP HSP

DEP : DEP
bits : 0 - 0 (1 bit)
access : read-write

VSP : VSP
bits : 1 - 1 (1 bit)
access : read-write

HSP : HSP
bits : 2 - 2 (1 bit)
access : read-write


DSI_VCCCR (VCCCR)

DSI Host video chunks current configuration register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VCCCR DSI_VCCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUMC

NUMC : NUMC
bits : 0 - 12 (13 bit)
access : read-only


DSI_VNPCCR (VNPCCR)

DSI Host video null packet current configuration register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VNPCCR DSI_VNPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPSIZE

NPSIZE : NPSIZE
bits : 0 - 12 (13 bit)
access : read-only


DSI_VHSACCR (VHSACCR)

DSI Host video HSA current configuration register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VHSACCR DSI_VHSACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSA

HSA : HSA
bits : 0 - 11 (12 bit)
access : read-only


DSI_VHBPCCR (VHBPCCR)

DSI Host video HBP current configuration register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VHBPCCR DSI_VHBPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBP

HBP : HBP
bits : 0 - 11 (12 bit)
access : read-only


DSI_VLCCR (VLCCR)

DSI Host video line current configuration register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VLCCR DSI_VLCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLINE

HLINE : HLINE
bits : 0 - 14 (15 bit)
access : read-only


DSI_VVSACCR (VVSACCR)

DSI Host video VSA current configuration register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVSACCR DSI_VVSACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSA

VSA : VSA
bits : 0 - 9 (10 bit)
access : read-only


DSI_VVBPCCR (VVBPCCR)

DSI Host video VBP current configuration register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVBPCCR DSI_VVBPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBP

VBP : VBP
bits : 0 - 9 (10 bit)
access : read-only


DSI_VVFPCCR (VVFPCCR)

DSI Host video VFP current configuration register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVFPCCR DSI_VVFPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFP

VFP : VFP
bits : 0 - 9 (10 bit)
access : read-only


DSI_VVACCR (VVACCR)

DSI Host video VA current configuration register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVACCR DSI_VVACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VA

VA : VA
bits : 0 - 13 (14 bit)
access : read-only


DSI_LPMCR (LPMCR)

DSI Host low-power mode configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LPMCR DSI_LPMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLPSIZE LPSIZE

VLPSIZE : VLPSIZE
bits : 0 - 7 (8 bit)
access : read-write

LPSIZE : LPSIZE
bits : 16 - 23 (8 bit)
access : read-write


DSI_PCR (PCR)

DSI Host protocol configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCR DSI_PCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETTXE ETRXE BTAE ECCRXE CRCRXE

ETTXE : ETTXE
bits : 0 - 0 (1 bit)
access : read-write

ETRXE : ETRXE
bits : 1 - 1 (1 bit)
access : read-write

BTAE : BTAE
bits : 2 - 2 (1 bit)
access : read-write

ECCRXE : ECCRXE
bits : 3 - 3 (1 bit)
access : read-write

CRCRXE : CRCRXE
bits : 4 - 4 (1 bit)
access : read-write


DSI_GVCIDR (GVCIDR)

DSI Host generic VCID register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_GVCIDR DSI_GVCIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : VCID
bits : 0 - 1 (2 bit)
access : read-only


DSI_MCR (MCR)

DSI Host mode configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_MCR DSI_MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDM

CMDM : CMDM
bits : 0 - 0 (1 bit)
access : read-write


DSI_VMCR (VMCR)

DSI Host video mode configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VMCR DSI_VMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMT LPVSAE LPVBPE LPVFPE LPVAE LPHBPE LPHFPE FBTAAE LPCE PGE PGM PGO

VMT : VMT
bits : 0 - 1 (2 bit)
access : read-write

LPVSAE : LPVSAE
bits : 8 - 8 (1 bit)
access : read-write

LPVBPE : LPVBPE
bits : 9 - 9 (1 bit)
access : read-write

LPVFPE : LPVFPE
bits : 10 - 10 (1 bit)
access : read-write

LPVAE : LPVAE
bits : 11 - 11 (1 bit)
access : read-write

LPHBPE : LPHBPE
bits : 12 - 12 (1 bit)
access : read-write

LPHFPE : LPHFPE
bits : 13 - 13 (1 bit)
access : read-write

FBTAAE : FBTAAE
bits : 14 - 14 (1 bit)
access : read-write

LPCE : LPCE
bits : 15 - 15 (1 bit)
access : read-write

PGE : PGE
bits : 16 - 16 (1 bit)
access : read-write

PGM : PGM
bits : 20 - 20 (1 bit)
access : read-write

PGO : PGO
bits : 24 - 24 (1 bit)
access : read-write


DSI_VPCR (VPCR)

DSI Host video packet configuration register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VPCR DSI_VPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPSIZE

VPSIZE : VPSIZE
bits : 0 - 13 (14 bit)
access : read-write


DSI_CR (CR)

DSI Host control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CR DSI_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : EN
bits : 0 - 0 (1 bit)
access : read-write


DSI_VCCR (VCCR)

DSI Host video chunks configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VCCR DSI_VCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUMC

NUMC : NUMC
bits : 0 - 12 (13 bit)
access : read-write


DSI_WCFGR (WCFGR)

DSI wrapper configuration register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WCFGR DSI_WCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSIM COLMUX TESRC TEPOL AR VSPOL

DSIM : DSIM
bits : 0 - 0 (1 bit)
access : read-write

COLMUX : COLMUX
bits : 1 - 3 (3 bit)
access : read-write

TESRC : TESRC
bits : 4 - 4 (1 bit)
access : read-write

TEPOL : TEPOL
bits : 5 - 5 (1 bit)
access : read-write

AR : AR
bits : 6 - 6 (1 bit)
access : read-write

VSPOL : VSPOL
bits : 7 - 7 (1 bit)
access : read-write


DSI_WCR (WCR)

DSI wrapper control register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WCR DSI_WCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLM SHTDN LTDCEN DSIEN

COLM : COLM
bits : 0 - 0 (1 bit)
access : read-write

SHTDN : SHTDN
bits : 1 - 1 (1 bit)
access : read-write

LTDCEN : LTDCEN
bits : 2 - 2 (1 bit)
access : read-write

DSIEN : DSIEN
bits : 3 - 3 (1 bit)
access : read-write


DSI_WIER (WIER)

DSI wrapper interrupt enable register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WIER DSI_WIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEIE ERIE PLLLIE PLLUIE RRIE

TEIE : TEIE
bits : 0 - 0 (1 bit)
access : read-write

ERIE : ERIE
bits : 1 - 1 (1 bit)
access : read-write

PLLLIE : PLLLIE
bits : 9 - 9 (1 bit)
access : read-write

PLLUIE : PLLUIE
bits : 10 - 10 (1 bit)
access : read-write

RRIE : RRIE
bits : 13 - 13 (1 bit)
access : read-write


DSI_WISR (WISR)

DSI wrapper interrupt and status register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_WISR DSI_WISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEIF ERIF BUSY PLLLS PLLLIF PLLUIF RRS RRIF

TEIF : TEIF
bits : 0 - 0 (1 bit)
access : read-only

ERIF : ERIF
bits : 1 - 1 (1 bit)
access : read-only

BUSY : BUSY
bits : 2 - 2 (1 bit)
access : read-only

PLLLS : PLLLS
bits : 8 - 8 (1 bit)
access : read-only

PLLLIF : PLLLIF
bits : 9 - 9 (1 bit)
access : read-only

PLLUIF : PLLUIF
bits : 10 - 10 (1 bit)
access : read-only

RRS : RRS
bits : 12 - 12 (1 bit)
access : read-only

RRIF : RRIF
bits : 13 - 13 (1 bit)
access : read-only


DSI_WIFCR (WIFCR)

DSI wrapper interrupt flag clear register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WIFCR DSI_WIFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEIF CERIF CPLLLIF CPLLUIF CRRIF

CTEIF : CTEIF
bits : 0 - 0 (1 bit)
access : write-only

CERIF : CERIF
bits : 1 - 1 (1 bit)
access : write-only

CPLLLIF : CPLLLIF
bits : 9 - 9 (1 bit)
access : write-only

CPLLUIF : CPLLUIF
bits : 10 - 10 (1 bit)
access : write-only

CRRIF : CRRIF
bits : 13 - 13 (1 bit)
access : write-only


DSI_WPCR0 (WPCR0)

DSI wrapper PHY configuration register 0
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR0 DSI_WPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIX4 SWCL SWDL0 SWDL1 HSICL HSIDL0 HSIDL1 FTXSMCL FTXSMDL CDOFFDL TDDL

UIX4 : UIX4
bits : 0 - 5 (6 bit)
access : read-write

SWCL : SWCL
bits : 6 - 6 (1 bit)
access : read-write

SWDL0 : SWDL0
bits : 7 - 7 (1 bit)
access : read-write

SWDL1 : SWDL1
bits : 8 - 8 (1 bit)
access : read-write

HSICL : HSICL
bits : 9 - 9 (1 bit)
access : read-write

HSIDL0 : HSIDL0
bits : 10 - 10 (1 bit)
access : read-write

HSIDL1 : HSIDL1
bits : 11 - 11 (1 bit)
access : read-write

FTXSMCL : FTXSMCL
bits : 12 - 12 (1 bit)
access : read-write

FTXSMDL : FTXSMDL
bits : 13 - 13 (1 bit)
access : read-write

CDOFFDL : CDOFFDL
bits : 14 - 14 (1 bit)
access : read-write

TDDL : TDDL
bits : 16 - 16 (1 bit)
access : read-write


DSI_WPCR1 (WPCR1)

This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR1 DSI_WPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SKEWCL SKEWDL LPTXSRCL LPTXSRDL SDDCCL SDDCDL HSTXSRUCL HSTXSRDCL HSTXSRUDL HSTXSRDDL

SKEWCL : SKEWCL
bits : 0 - 1 (2 bit)
access : read-write

SKEWDL : SKEWDL
bits : 2 - 3 (2 bit)
access : read-write

LPTXSRCL : LPTXSRCL
bits : 6 - 7 (2 bit)
access : read-write

LPTXSRDL : LPTXSRDL
bits : 8 - 9 (2 bit)
access : read-write

SDDCCL : SDDCCL
bits : 12 - 12 (1 bit)
access : read-write

SDDCDL : SDDCDL
bits : 13 - 13 (1 bit)
access : read-write

HSTXSRUCL : HSTXSRUCL
bits : 16 - 16 (1 bit)
access : read-write

HSTXSRDCL : HSTXSRDCL
bits : 17 - 17 (1 bit)
access : read-write

HSTXSRUDL : HSTXSRUDL
bits : 18 - 18 (1 bit)
access : read-write

HSTXSRDDL : HSTXSRDDL
bits : 19 - 19 (1 bit)
access : read-write


DSI_WRPCR (WRPCR)

DSI wrapper regulator and PLL control register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WRPCR DSI_WRPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLEN NDIV IDF ODF REGEN BGREN

PLLEN : PLLEN
bits : 0 - 0 (1 bit)
access : read-write

NDIV : NDIV
bits : 2 - 8 (7 bit)
access : read-write

IDF : IDF
bits : 11 - 14 (4 bit)
access : read-write

ODF : ODF
bits : 16 - 17 (2 bit)
access : read-write

REGEN : REGEN
bits : 24 - 24 (1 bit)
access : read-write

BGREN : BGREN
bits : 28 - 28 (1 bit)
access : read-write


DSI_VNPCR (VNPCR)

DSI Host video null packet configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VNPCR DSI_VNPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPSIZE

NPSIZE : NPSIZE
bits : 0 - 12 (13 bit)
access : read-write


DSI_VHSACR (VHSACR)

DSI Host video HSA configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VHSACR DSI_VHSACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSA

HSA : HSA
bits : 0 - 11 (12 bit)
access : read-write


DSI_VHBPCR (VHBPCR)

DSI Host video HBP configuration register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VHBPCR DSI_VHBPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBP

HBP : HBP
bits : 0 - 11 (12 bit)
access : read-write


DSI_VLCR (VLCR)

DSI Host video line configuration register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VLCR DSI_VLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLINE

HLINE : HLINE
bits : 0 - 14 (15 bit)
access : read-write


DSI_VVSACR (VVSACR)

DSI Host video VSA configuration register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVSACR DSI_VVSACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSA

VSA : VSA
bits : 0 - 9 (10 bit)
access : read-write


DSI_VVBPCR (VVBPCR)

DSI Host video VBP configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVBPCR DSI_VVBPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBP

VBP : VBP
bits : 0 - 9 (10 bit)
access : read-write


DSI_VVFPCR (VVFPCR)

DSI Host video VFP configuration register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVFPCR DSI_VVFPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFP

VFP : VFP
bits : 0 - 9 (10 bit)
access : read-write


DSI_VVACR (VVACR)

DSI Host video VA configuration register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVACR DSI_VVACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VA

VA : VA
bits : 0 - 13 (14 bit)
access : read-write


DSI_LCCR (LCCR)

DSI Host LTDC command configuration register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LCCR DSI_LCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDSIZE

CMDSIZE : CMDSIZE
bits : 0 - 15 (16 bit)
access : read-write


DSI_CMCR (CMCR)

DSI Host command mode configuration register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CMCR DSI_CMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEARE ARE GSW0TX GSW1TX GSW2TX GSR0TX GSR1TX GSR2TX GLWTX DSW0TX DSW1TX DSR0TX DLWTX MRDPS

TEARE : TEARE
bits : 0 - 0 (1 bit)
access : read-write

ARE : ARE
bits : 1 - 1 (1 bit)
access : read-write

GSW0TX : GSW0TX
bits : 8 - 8 (1 bit)
access : read-write

GSW1TX : GSW1TX
bits : 9 - 9 (1 bit)
access : read-write

GSW2TX : GSW2TX
bits : 10 - 10 (1 bit)
access : read-write

GSR0TX : GSR0TX
bits : 11 - 11 (1 bit)
access : read-write

GSR1TX : GSR1TX
bits : 12 - 12 (1 bit)
access : read-write

GSR2TX : GSR2TX
bits : 13 - 13 (1 bit)
access : read-write

GLWTX : GLWTX
bits : 14 - 14 (1 bit)
access : read-write

DSW0TX : DSW0TX
bits : 16 - 16 (1 bit)
access : read-write

DSW1TX : DSW1TX
bits : 17 - 17 (1 bit)
access : read-write

DSR0TX : DSR0TX
bits : 18 - 18 (1 bit)
access : read-write

DLWTX : DLWTX
bits : 19 - 19 (1 bit)
access : read-write

MRDPS : MRDPS
bits : 24 - 24 (1 bit)
access : read-write


DSI_GHCR (GHCR)

DSI Host generic header configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_GHCR DSI_GHCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT VCID WCLSB WCMSB

DT : DT
bits : 0 - 5 (6 bit)
access : read-write

VCID : VCID
bits : 6 - 7 (2 bit)
access : read-write

WCLSB : WCLSB
bits : 8 - 15 (8 bit)
access : read-write

WCMSB : WCMSB
bits : 16 - 23 (8 bit)
access : read-write


DSI_GPDR (GPDR)

DSI Host generic payload data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_GPDR DSI_GPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1 DATA2 DATA3 DATA4

DATA1 : DATA1
bits : 0 - 7 (8 bit)
access : read-write

DATA2 : DATA2
bits : 8 - 15 (8 bit)
access : read-write

DATA3 : DATA3
bits : 16 - 23 (8 bit)
access : read-write

DATA4 : DATA4
bits : 24 - 31 (8 bit)
access : read-write


DSI_GPSR (GPSR)

DSI Host generic packet status register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_GPSR DSI_GPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDFE CMDFF PWRFE PWRFF PRDFE PRDFF RCB

CMDFE : CMDFE
bits : 0 - 0 (1 bit)
access : read-only

CMDFF : CMDFF
bits : 1 - 1 (1 bit)
access : read-only

PWRFE : PWRFE
bits : 2 - 2 (1 bit)
access : read-only

PWRFF : PWRFF
bits : 3 - 3 (1 bit)
access : read-only

PRDFE : PRDFE
bits : 4 - 4 (1 bit)
access : read-only

PRDFF : PRDFF
bits : 5 - 5 (1 bit)
access : read-only

RCB : RCB
bits : 6 - 6 (1 bit)
access : read-only


DSI_TCCR0 (TCCR0)

DSI Host timeout counter configuration register 0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR0 DSI_TCCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPRX_TOCNT HSTX_TOCNT

LPRX_TOCNT : LPRX_TOCNT
bits : 0 - 15 (16 bit)
access : read-write

HSTX_TOCNT : HSTX_TOCNT
bits : 16 - 31 (16 bit)
access : read-write


DSI_TCCR1 (TCCR1)

DSI Host timeout counter configuration register 1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR1 DSI_TCCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSRD_TOCNT

HSRD_TOCNT : HSRD_TOCNT
bits : 0 - 15 (16 bit)
access : read-write


DSI_HWCFGR (HWCFGR)

DSI Host hardware configuration register
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_HWCFGR DSI_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TECHNO FIFOSIZE

TECHNO : TECHNO
bits : 0 - 3 (4 bit)
access : read-only

FIFOSIZE : FIFOSIZE
bits : 4 - 15 (12 bit)
access : read-only


DSI_VERR (VERR)

DSI Host version register
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VERR DSI_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)
access : read-only

MAJREV : MAJREV
bits : 4 - 7 (4 bit)
access : read-only


DSI_IPIDR (IPIDR)

DSI Host identification register
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_IPIDR DSI_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)
access : read-only


DSI_SIDR (SIDR)

DSI Host size identification register
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_SIDR DSI_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)
access : read-only


DSI_CCR (CCR)

DSI Host clock control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CCR DSI_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXECKDIV TOCKDIV

TXECKDIV : TXECKDIV
bits : 0 - 7 (8 bit)
access : read-write

TOCKDIV : TOCKDIV
bits : 8 - 15 (8 bit)
access : read-write


DSI_TCCR2 (TCCR2)

DSI Host timeout counter configuration register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR2 DSI_TCCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPRD_TOCNT

LPRD_TOCNT : LPRD_TOCNT
bits : 0 - 15 (16 bit)
access : read-write


DSI_TCCR3 (TCCR3)

DSI Host timeout counter configuration register 3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR3 DSI_TCCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSWR_TOCNT PM

HSWR_TOCNT : HSWR_TOCNT
bits : 0 - 15 (16 bit)
access : read-write

PM : PM
bits : 24 - 24 (1 bit)
access : read-write


DSI_TCCR4 (TCCR4)

DSI Host timeout counter configuration register 4
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR4 DSI_TCCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPWR_TOCNT

LPWR_TOCNT : LPWR_TOCNT
bits : 0 - 15 (16 bit)
access : read-write


DSI_TCCR5 (TCCR5)

DSI Host timeout counter configuration register 5
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR5 DSI_TCCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTA_TOCNT

BTA_TOCNT : BTA_TOCNT
bits : 0 - 15 (16 bit)
access : read-write


DSI_CLCR (CLCR)

DSI Host clock lane configuration register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CLCR DSI_CLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPCC ACR

DPCC : DPCC
bits : 0 - 0 (1 bit)
access : read-write

ACR : ACR
bits : 1 - 1 (1 bit)
access : read-write


DSI_CLTCR (CLTCR)

DSI Host clock lane timer configuration register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CLTCR DSI_CLTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LP2HS_TIME HS2LP_TIME

LP2HS_TIME : LP2HS_TIME
bits : 0 - 9 (10 bit)
access : read-write

HS2LP_TIME : HS2LP_TIME
bits : 16 - 25 (10 bit)
access : read-write


DSI_DLTCR (DLTCR)

DSI Host data lane timer configuration register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_DLTCR DSI_DLTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LP2HS_TIME HS2LP_TIME

LP2HS_TIME : LP2HS_TIME
bits : 0 - 9 (10 bit)
access : read-write

HS2LP_TIME : HS2LP_TIME
bits : 16 - 25 (10 bit)
access : read-write


DSI_PCTLR (PCTLR)

DSI Host PHY control register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCTLR DSI_PCTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN CKE

DEN : DEN
bits : 1 - 1 (1 bit)
access : read-write

CKE : CKE
bits : 2 - 2 (1 bit)
access : read-write


DSI_PCONFR (PCONFR)

DSI Host PHY configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCONFR DSI_PCONFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NL SW_TIME

NL : NL
bits : 0 - 1 (2 bit)
access : read-write

SW_TIME : SW_TIME
bits : 8 - 15 (8 bit)
access : read-write


DSI_PUCR (PUCR)

DSI Host PHY ULPS control register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PUCR DSI_PUCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 URCL UECL URDL UEDL

URCL : URCL
bits : 0 - 0 (1 bit)
access : read-write

UECL : UECL
bits : 1 - 1 (1 bit)
access : read-write

URDL : URDL
bits : 2 - 2 (1 bit)
access : read-write

UEDL : UEDL
bits : 3 - 3 (1 bit)
access : read-write


DSI_PTTCR (PTTCR)

DSI Host PHY TX triggers configuration register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PTTCR DSI_PTTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_TRIG

TX_TRIG : TX_TRIG
bits : 0 - 3 (4 bit)
access : read-write


DSI_PSR (PSR)

DSI Host PHY status register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_PSR DSI_PSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD PSSC UANC PSS0 UAN0 RUE0 PSS1 UAN1

PD : PD
bits : 1 - 1 (1 bit)
access : read-only

PSSC : PSSC
bits : 2 - 2 (1 bit)
access : read-only

UANC : UANC
bits : 3 - 3 (1 bit)
access : read-only

PSS0 : PSS0
bits : 4 - 4 (1 bit)
access : read-only

UAN0 : UAN0
bits : 5 - 5 (1 bit)
access : read-only

RUE0 : RUE0
bits : 6 - 6 (1 bit)
access : read-only

PSS1 : PSS1
bits : 7 - 7 (1 bit)
access : read-only

UAN1 : UAN1
bits : 8 - 8 (1 bit)
access : read-only


DSI_ISR0 (ISR0)

DSI Host interrupt and status register 0
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_ISR0 DSI_ISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AE0 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 PE0 PE1 PE2 PE3 PE4

AE0 : AE0
bits : 0 - 0 (1 bit)
access : read-only

AE1 : AE1
bits : 1 - 1 (1 bit)
access : read-only

AE2 : AE2
bits : 2 - 2 (1 bit)
access : read-only

AE3 : AE3
bits : 3 - 3 (1 bit)
access : read-only

AE4 : AE4
bits : 4 - 4 (1 bit)
access : read-only

AE5 : AE5
bits : 5 - 5 (1 bit)
access : read-only

AE6 : AE6
bits : 6 - 6 (1 bit)
access : read-only

AE7 : AE7
bits : 7 - 7 (1 bit)
access : read-only

AE8 : AE8
bits : 8 - 8 (1 bit)
access : read-only

AE9 : AE9
bits : 9 - 9 (1 bit)
access : read-only

AE10 : AE10
bits : 10 - 10 (1 bit)
access : read-only

AE11 : AE11
bits : 11 - 11 (1 bit)
access : read-only

AE12 : AE12
bits : 12 - 12 (1 bit)
access : read-only

AE13 : AE13
bits : 13 - 13 (1 bit)
access : read-only

AE14 : AE14
bits : 14 - 14 (1 bit)
access : read-only

AE15 : AE15
bits : 15 - 15 (1 bit)
access : read-only

PE0 : PE0
bits : 16 - 16 (1 bit)
access : read-only

PE1 : PE1
bits : 17 - 17 (1 bit)
access : read-only

PE2 : PE2
bits : 18 - 18 (1 bit)
access : read-only

PE3 : PE3
bits : 19 - 19 (1 bit)
access : read-only

PE4 : PE4
bits : 20 - 20 (1 bit)
access : read-only


DSI_LVCIDR (LVCIDR)

DSI Host LTDC VCID register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LVCIDR DSI_LVCIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : VCID
bits : 0 - 1 (2 bit)
access : read-write


DSI_ISR1 (ISR1)

DSI Host interrupt and status register 1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_ISR1 DSI_ISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOHSTX TOLPRX ECCSE ECCME CRCE PSE EOTPE LPWRE GCWRE GPWRE GPTXE GPRDE GPRXE

TOHSTX : TOHSTX
bits : 0 - 0 (1 bit)
access : read-only

TOLPRX : TOLPRX
bits : 1 - 1 (1 bit)
access : read-only

ECCSE : ECCSE
bits : 2 - 2 (1 bit)
access : read-only

ECCME : ECCME
bits : 3 - 3 (1 bit)
access : read-only

CRCE : CRCE
bits : 4 - 4 (1 bit)
access : read-only

PSE : PSE
bits : 5 - 5 (1 bit)
access : read-only

EOTPE : EOTPE
bits : 6 - 6 (1 bit)
access : read-only

LPWRE : LPWRE
bits : 7 - 7 (1 bit)
access : read-only

GCWRE : GCWRE
bits : 8 - 8 (1 bit)
access : read-only

GPWRE : GPWRE
bits : 9 - 9 (1 bit)
access : read-only

GPTXE : GPTXE
bits : 10 - 10 (1 bit)
access : read-only

GPRDE : GPRDE
bits : 11 - 11 (1 bit)
access : read-only

GPRXE : GPRXE
bits : 12 - 12 (1 bit)
access : read-only


DSI_IER0 (IER0)

DSI Host interrupt enable register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_IER0 DSI_IER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AE0IE AE1IE AE2IE AE3IE AE4IE AE5IE AE6IE AE7IE AE8IE AE9IE AE10IE AE11IE AE12IE AE13IE AE14IE AE15IE PE0IE PE1IE PE2IE PE3IE PE4IE

AE0IE : AE0IE
bits : 0 - 0 (1 bit)
access : read-write

AE1IE : AE1IE
bits : 1 - 1 (1 bit)
access : read-write

AE2IE : AE2IE
bits : 2 - 2 (1 bit)
access : read-write

AE3IE : AE3IE
bits : 3 - 3 (1 bit)
access : read-write

AE4IE : AE4IE
bits : 4 - 4 (1 bit)
access : read-write

AE5IE : AE5IE
bits : 5 - 5 (1 bit)
access : read-write

AE6IE : AE6IE
bits : 6 - 6 (1 bit)
access : read-write

AE7IE : AE7IE
bits : 7 - 7 (1 bit)
access : read-write

AE8IE : AE8IE
bits : 8 - 8 (1 bit)
access : read-write

AE9IE : AE9IE
bits : 9 - 9 (1 bit)
access : read-write

AE10IE : AE10IE
bits : 10 - 10 (1 bit)
access : read-write

AE11IE : AE11IE
bits : 11 - 11 (1 bit)
access : read-write

AE12IE : AE12IE
bits : 12 - 12 (1 bit)
access : read-write

AE13IE : AE13IE
bits : 13 - 13 (1 bit)
access : read-write

AE14IE : AE14IE
bits : 14 - 14 (1 bit)
access : read-write

AE15IE : AE15IE
bits : 15 - 15 (1 bit)
access : read-write

PE0IE : PE0IE
bits : 16 - 16 (1 bit)
access : read-write

PE1IE : PE1IE
bits : 17 - 17 (1 bit)
access : read-write

PE2IE : PE2IE
bits : 18 - 18 (1 bit)
access : read-write

PE3IE : PE3IE
bits : 19 - 19 (1 bit)
access : read-write

PE4IE : PE4IE
bits : 20 - 20 (1 bit)
access : read-write


DSI_IER1 (IER1)

DSI Host interrupt enable register 1
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_IER1 DSI_IER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOHSTXIE TOLPRXIE ECCSEIE ECCMEIE CRCEIE PSEIE EOTPEIE LPWREIE GCWREIE GPWREIE GPTXEIE GPRDEIE GPRXEIE

TOHSTXIE : TOHSTXIE
bits : 0 - 0 (1 bit)
access : read-write

TOLPRXIE : TOLPRXIE
bits : 1 - 1 (1 bit)
access : read-write

ECCSEIE : ECCSEIE
bits : 2 - 2 (1 bit)
access : read-write

ECCMEIE : ECCMEIE
bits : 3 - 3 (1 bit)
access : read-write

CRCEIE : CRCEIE
bits : 4 - 4 (1 bit)
access : read-write

PSEIE : PSEIE
bits : 5 - 5 (1 bit)
access : read-write

EOTPEIE : EOTPEIE
bits : 6 - 6 (1 bit)
access : read-write

LPWREIE : LPWREIE
bits : 7 - 7 (1 bit)
access : read-write

GCWREIE : GCWREIE
bits : 8 - 8 (1 bit)
access : read-write

GPWREIE : GPWREIE
bits : 9 - 9 (1 bit)
access : read-write

GPTXEIE : GPTXEIE
bits : 10 - 10 (1 bit)
access : read-write

GPRDEIE : GPRDEIE
bits : 11 - 11 (1 bit)
access : read-write

GPRXEIE : GPRXEIE
bits : 12 - 12 (1 bit)
access : read-write


DSI_FIR0 (FIR0)

DSI Host force interrupt register 0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_FIR0 DSI_FIR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAE0 FAE1 FAE2 FAE3 FAE4 FAE5 FAE6 FAE7 FAE8 FAE9 FAE10 FAE11 FAE12 FAE13 FAE14 FAE15 FPE0 FPE1 FPE2 FPE3 FPE4

FAE0 : FAE0
bits : 0 - 0 (1 bit)
access : write-only

FAE1 : FAE1
bits : 1 - 1 (1 bit)
access : write-only

FAE2 : FAE2
bits : 2 - 2 (1 bit)
access : write-only

FAE3 : FAE3
bits : 3 - 3 (1 bit)
access : write-only

FAE4 : FAE4
bits : 4 - 4 (1 bit)
access : write-only

FAE5 : FAE5
bits : 5 - 5 (1 bit)
access : write-only

FAE6 : FAE6
bits : 6 - 6 (1 bit)
access : write-only

FAE7 : FAE7
bits : 7 - 7 (1 bit)
access : write-only

FAE8 : FAE8
bits : 8 - 8 (1 bit)
access : write-only

FAE9 : FAE9
bits : 9 - 9 (1 bit)
access : write-only

FAE10 : FAE10
bits : 10 - 10 (1 bit)
access : write-only

FAE11 : FAE11
bits : 11 - 11 (1 bit)
access : write-only

FAE12 : FAE12
bits : 12 - 12 (1 bit)
access : write-only

FAE13 : FAE13
bits : 13 - 13 (1 bit)
access : write-only

FAE14 : FAE14
bits : 14 - 14 (1 bit)
access : write-only

FAE15 : FAE15
bits : 15 - 15 (1 bit)
access : write-only

FPE0 : FPE0
bits : 16 - 16 (1 bit)
access : write-only

FPE1 : FPE1
bits : 17 - 17 (1 bit)
access : write-only

FPE2 : FPE2
bits : 18 - 18 (1 bit)
access : write-only

FPE3 : FPE3
bits : 19 - 19 (1 bit)
access : write-only

FPE4 : FPE4
bits : 20 - 20 (1 bit)
access : write-only


DSI_FIR1 (FIR1)

DSI Host force interrupt register 1
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_FIR1 DSI_FIR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTOHSTX FTOLPRX FECCSE FECCME FCRCE FPSE FEOTPE FLPWRE FGCWRE FGPWRE FGPTXE FGPRDE FGPRXE

FTOHSTX : FTOHSTX
bits : 0 - 0 (1 bit)
access : write-only

FTOLPRX : FTOLPRX
bits : 1 - 1 (1 bit)
access : write-only

FECCSE : FECCSE
bits : 2 - 2 (1 bit)
access : write-only

FECCME : FECCME
bits : 3 - 3 (1 bit)
access : write-only

FCRCE : FCRCE
bits : 4 - 4 (1 bit)
access : write-only

FPSE : FPSE
bits : 5 - 5 (1 bit)
access : write-only

FEOTPE : FEOTPE
bits : 6 - 6 (1 bit)
access : write-only

FLPWRE : FLPWRE
bits : 7 - 7 (1 bit)
access : write-only

FGCWRE : FGCWRE
bits : 8 - 8 (1 bit)
access : write-only

FGPWRE : FGPWRE
bits : 9 - 9 (1 bit)
access : write-only

FGPTXE : FGPTXE
bits : 10 - 10 (1 bit)
access : write-only

FGPRDE : FGPRDE
bits : 11 - 11 (1 bit)
access : write-only

FGPRXE : FGPRXE
bits : 12 - 12 (1 bit)
access : write-only


DSI_DLTRCR (DLTRCR)

DSI Host data lane timer read configuration register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_DLTRCR DSI_DLTRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRD_TIME

MRD_TIME : MRD_TIME
bits : 0 - 14 (15 bit)
access : read-write



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