\n
address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected
DSI Host version register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : VERSION
bits : 0 - 31 (32 bit)
access : read-only
DSI Host LTDC color coding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLC : COLC
bits : 0 - 3 (4 bit)
access : read-write
LPE : LPE
bits : 8 - 8 (1 bit)
access : read-write
DSI Host video shadow control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
UR : UR
bits : 8 - 8 (1 bit)
access : read-write
DSI Host LTDC current VCID register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCID : VCID
bits : 0 - 1 (2 bit)
access : read-write
DSI Host LTDC current color coding register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COLC : COLC
bits : 0 - 3 (4 bit)
access : read-only
LPE : LPE
bits : 8 - 8 (1 bit)
access : read-only
DSI Host low-power mode current configuration register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VLPSIZE : VLPSIZE
bits : 0 - 7 (8 bit)
access : read-only
LPSIZE : LPSIZE
bits : 16 - 23 (8 bit)
access : read-only
DSI Host video mode current configuration register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VMT : VMT
bits : 0 - 1 (2 bit)
access : read-only
LPVSAE : LPVSAE
bits : 2 - 2 (1 bit)
access : read-only
LPVBPE : LPVBPE
bits : 3 - 3 (1 bit)
access : read-only
LPVFPE : LPVFPE
bits : 4 - 4 (1 bit)
access : read-only
LPVAE : LPVAE
bits : 5 - 5 (1 bit)
access : read-only
LPHBPE : LPHBPE
bits : 6 - 6 (1 bit)
access : read-only
LPHFE : LPHFE
bits : 7 - 7 (1 bit)
access : read-only
FBTAAE : FBTAAE
bits : 8 - 8 (1 bit)
access : read-only
LPCE : LPCE
bits : 9 - 9 (1 bit)
access : read-only
DSI Host video packet current configuration register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VPSIZE : VPSIZE
bits : 0 - 13 (14 bit)
access : read-only
DSI Host LTDC polarity configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEP : DEP
bits : 0 - 0 (1 bit)
access : read-write
VSP : VSP
bits : 1 - 1 (1 bit)
access : read-write
HSP : HSP
bits : 2 - 2 (1 bit)
access : read-write
DSI Host video chunks current configuration register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NUMC : NUMC
bits : 0 - 12 (13 bit)
access : read-only
DSI Host video null packet current configuration register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NPSIZE : NPSIZE
bits : 0 - 12 (13 bit)
access : read-only
DSI Host video HSA current configuration register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HSA : HSA
bits : 0 - 11 (12 bit)
access : read-only
DSI Host video HBP current configuration register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HBP : HBP
bits : 0 - 11 (12 bit)
access : read-only
DSI Host video line current configuration register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HLINE : HLINE
bits : 0 - 14 (15 bit)
access : read-only
DSI Host video VSA current configuration register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VSA : VSA
bits : 0 - 9 (10 bit)
access : read-only
DSI Host video VBP current configuration register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VBP : VBP
bits : 0 - 9 (10 bit)
access : read-only
DSI Host video VFP current configuration register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VFP : VFP
bits : 0 - 9 (10 bit)
access : read-only
DSI Host video VA current configuration register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VA : VA
bits : 0 - 13 (14 bit)
access : read-only
DSI Host low-power mode configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLPSIZE : VLPSIZE
bits : 0 - 7 (8 bit)
access : read-write
LPSIZE : LPSIZE
bits : 16 - 23 (8 bit)
access : read-write
DSI Host protocol configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETTXE : ETTXE
bits : 0 - 0 (1 bit)
access : read-write
ETRXE : ETRXE
bits : 1 - 1 (1 bit)
access : read-write
BTAE : BTAE
bits : 2 - 2 (1 bit)
access : read-write
ECCRXE : ECCRXE
bits : 3 - 3 (1 bit)
access : read-write
CRCRXE : CRCRXE
bits : 4 - 4 (1 bit)
access : read-write
DSI Host generic VCID register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VCID : VCID
bits : 0 - 1 (2 bit)
access : read-only
DSI Host mode configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDM : CMDM
bits : 0 - 0 (1 bit)
access : read-write
DSI Host video mode configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VMT : VMT
bits : 0 - 1 (2 bit)
access : read-write
LPVSAE : LPVSAE
bits : 8 - 8 (1 bit)
access : read-write
LPVBPE : LPVBPE
bits : 9 - 9 (1 bit)
access : read-write
LPVFPE : LPVFPE
bits : 10 - 10 (1 bit)
access : read-write
LPVAE : LPVAE
bits : 11 - 11 (1 bit)
access : read-write
LPHBPE : LPHBPE
bits : 12 - 12 (1 bit)
access : read-write
LPHFPE : LPHFPE
bits : 13 - 13 (1 bit)
access : read-write
FBTAAE : FBTAAE
bits : 14 - 14 (1 bit)
access : read-write
LPCE : LPCE
bits : 15 - 15 (1 bit)
access : read-write
PGE : PGE
bits : 16 - 16 (1 bit)
access : read-write
PGM : PGM
bits : 20 - 20 (1 bit)
access : read-write
PGO : PGO
bits : 24 - 24 (1 bit)
access : read-write
DSI Host video packet configuration register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VPSIZE : VPSIZE
bits : 0 - 13 (14 bit)
access : read-write
DSI Host control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
DSI Host video chunks configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMC : NUMC
bits : 0 - 12 (13 bit)
access : read-write
DSI wrapper configuration register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIM : DSIM
bits : 0 - 0 (1 bit)
access : read-write
COLMUX : COLMUX
bits : 1 - 3 (3 bit)
access : read-write
TESRC : TESRC
bits : 4 - 4 (1 bit)
access : read-write
TEPOL : TEPOL
bits : 5 - 5 (1 bit)
access : read-write
AR : AR
bits : 6 - 6 (1 bit)
access : read-write
VSPOL : VSPOL
bits : 7 - 7 (1 bit)
access : read-write
DSI wrapper control register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLM : COLM
bits : 0 - 0 (1 bit)
access : read-write
SHTDN : SHTDN
bits : 1 - 1 (1 bit)
access : read-write
LTDCEN : LTDCEN
bits : 2 - 2 (1 bit)
access : read-write
DSIEN : DSIEN
bits : 3 - 3 (1 bit)
access : read-write
DSI wrapper interrupt enable register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEIE : TEIE
bits : 0 - 0 (1 bit)
access : read-write
ERIE : ERIE
bits : 1 - 1 (1 bit)
access : read-write
PLLLIE : PLLLIE
bits : 9 - 9 (1 bit)
access : read-write
PLLUIE : PLLUIE
bits : 10 - 10 (1 bit)
access : read-write
RRIE : RRIE
bits : 13 - 13 (1 bit)
access : read-write
DSI wrapper interrupt and status register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
access : read-only
ERIF : ERIF
bits : 1 - 1 (1 bit)
access : read-only
BUSY : BUSY
bits : 2 - 2 (1 bit)
access : read-only
PLLLS : PLLLS
bits : 8 - 8 (1 bit)
access : read-only
PLLLIF : PLLLIF
bits : 9 - 9 (1 bit)
access : read-only
PLLUIF : PLLUIF
bits : 10 - 10 (1 bit)
access : read-only
RRS : RRS
bits : 12 - 12 (1 bit)
access : read-only
RRIF : RRIF
bits : 13 - 13 (1 bit)
access : read-only
DSI wrapper interrupt flag clear register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
access : write-only
CERIF : CERIF
bits : 1 - 1 (1 bit)
access : write-only
CPLLLIF : CPLLLIF
bits : 9 - 9 (1 bit)
access : write-only
CPLLUIF : CPLLUIF
bits : 10 - 10 (1 bit)
access : write-only
CRRIF : CRRIF
bits : 13 - 13 (1 bit)
access : write-only
DSI wrapper PHY configuration register 0
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIX4 : UIX4
bits : 0 - 5 (6 bit)
access : read-write
SWCL : SWCL
bits : 6 - 6 (1 bit)
access : read-write
SWDL0 : SWDL0
bits : 7 - 7 (1 bit)
access : read-write
SWDL1 : SWDL1
bits : 8 - 8 (1 bit)
access : read-write
HSICL : HSICL
bits : 9 - 9 (1 bit)
access : read-write
HSIDL0 : HSIDL0
bits : 10 - 10 (1 bit)
access : read-write
HSIDL1 : HSIDL1
bits : 11 - 11 (1 bit)
access : read-write
FTXSMCL : FTXSMCL
bits : 12 - 12 (1 bit)
access : read-write
FTXSMDL : FTXSMDL
bits : 13 - 13 (1 bit)
access : read-write
CDOFFDL : CDOFFDL
bits : 14 - 14 (1 bit)
access : read-write
TDDL : TDDL
bits : 16 - 16 (1 bit)
access : read-write
This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SKEWCL : SKEWCL
bits : 0 - 1 (2 bit)
access : read-write
SKEWDL : SKEWDL
bits : 2 - 3 (2 bit)
access : read-write
LPTXSRCL : LPTXSRCL
bits : 6 - 7 (2 bit)
access : read-write
LPTXSRDL : LPTXSRDL
bits : 8 - 9 (2 bit)
access : read-write
SDDCCL : SDDCCL
bits : 12 - 12 (1 bit)
access : read-write
SDDCDL : SDDCDL
bits : 13 - 13 (1 bit)
access : read-write
HSTXSRUCL : HSTXSRUCL
bits : 16 - 16 (1 bit)
access : read-write
HSTXSRDCL : HSTXSRDCL
bits : 17 - 17 (1 bit)
access : read-write
HSTXSRUDL : HSTXSRUDL
bits : 18 - 18 (1 bit)
access : read-write
HSTXSRDDL : HSTXSRDDL
bits : 19 - 19 (1 bit)
access : read-write
DSI wrapper regulator and PLL control register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLEN : PLLEN
bits : 0 - 0 (1 bit)
access : read-write
NDIV : NDIV
bits : 2 - 8 (7 bit)
access : read-write
IDF : IDF
bits : 11 - 14 (4 bit)
access : read-write
ODF : ODF
bits : 16 - 17 (2 bit)
access : read-write
REGEN : REGEN
bits : 24 - 24 (1 bit)
access : read-write
BGREN : BGREN
bits : 28 - 28 (1 bit)
access : read-write
DSI Host video null packet configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NPSIZE : NPSIZE
bits : 0 - 12 (13 bit)
access : read-write
DSI Host video HSA configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSA : HSA
bits : 0 - 11 (12 bit)
access : read-write
DSI Host video HBP configuration register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HBP : HBP
bits : 0 - 11 (12 bit)
access : read-write
DSI Host video line configuration register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HLINE : HLINE
bits : 0 - 14 (15 bit)
access : read-write
DSI Host video VSA configuration register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSA : VSA
bits : 0 - 9 (10 bit)
access : read-write
DSI Host video VBP configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBP : VBP
bits : 0 - 9 (10 bit)
access : read-write
DSI Host video VFP configuration register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VFP : VFP
bits : 0 - 9 (10 bit)
access : read-write
DSI Host video VA configuration register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VA : VA
bits : 0 - 13 (14 bit)
access : read-write
DSI Host LTDC command configuration register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDSIZE : CMDSIZE
bits : 0 - 15 (16 bit)
access : read-write
DSI Host command mode configuration register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEARE : TEARE
bits : 0 - 0 (1 bit)
access : read-write
ARE : ARE
bits : 1 - 1 (1 bit)
access : read-write
GSW0TX : GSW0TX
bits : 8 - 8 (1 bit)
access : read-write
GSW1TX : GSW1TX
bits : 9 - 9 (1 bit)
access : read-write
GSW2TX : GSW2TX
bits : 10 - 10 (1 bit)
access : read-write
GSR0TX : GSR0TX
bits : 11 - 11 (1 bit)
access : read-write
GSR1TX : GSR1TX
bits : 12 - 12 (1 bit)
access : read-write
GSR2TX : GSR2TX
bits : 13 - 13 (1 bit)
access : read-write
GLWTX : GLWTX
bits : 14 - 14 (1 bit)
access : read-write
DSW0TX : DSW0TX
bits : 16 - 16 (1 bit)
access : read-write
DSW1TX : DSW1TX
bits : 17 - 17 (1 bit)
access : read-write
DSR0TX : DSR0TX
bits : 18 - 18 (1 bit)
access : read-write
DLWTX : DLWTX
bits : 19 - 19 (1 bit)
access : read-write
MRDPS : MRDPS
bits : 24 - 24 (1 bit)
access : read-write
DSI Host generic header configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DT : DT
bits : 0 - 5 (6 bit)
access : read-write
VCID : VCID
bits : 6 - 7 (2 bit)
access : read-write
WCLSB : WCLSB
bits : 8 - 15 (8 bit)
access : read-write
WCMSB : WCMSB
bits : 16 - 23 (8 bit)
access : read-write
DSI Host generic payload data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA1 : DATA1
bits : 0 - 7 (8 bit)
access : read-write
DATA2 : DATA2
bits : 8 - 15 (8 bit)
access : read-write
DATA3 : DATA3
bits : 16 - 23 (8 bit)
access : read-write
DATA4 : DATA4
bits : 24 - 31 (8 bit)
access : read-write
DSI Host generic packet status register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDFE : CMDFE
bits : 0 - 0 (1 bit)
access : read-only
CMDFF : CMDFF
bits : 1 - 1 (1 bit)
access : read-only
PWRFE : PWRFE
bits : 2 - 2 (1 bit)
access : read-only
PWRFF : PWRFF
bits : 3 - 3 (1 bit)
access : read-only
PRDFE : PRDFE
bits : 4 - 4 (1 bit)
access : read-only
PRDFF : PRDFF
bits : 5 - 5 (1 bit)
access : read-only
RCB : RCB
bits : 6 - 6 (1 bit)
access : read-only
DSI Host timeout counter configuration register 0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPRX_TOCNT : LPRX_TOCNT
bits : 0 - 15 (16 bit)
access : read-write
HSTX_TOCNT : HSTX_TOCNT
bits : 16 - 31 (16 bit)
access : read-write
DSI Host timeout counter configuration register 1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSRD_TOCNT : HSRD_TOCNT
bits : 0 - 15 (16 bit)
access : read-write
DSI Host hardware configuration register
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TECHNO : TECHNO
bits : 0 - 3 (4 bit)
access : read-only
FIFOSIZE : FIFOSIZE
bits : 4 - 15 (12 bit)
access : read-only
DSI Host version register
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
access : read-only
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
access : read-only
DSI Host identification register
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
DSI Host size identification register
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
access : read-only
DSI Host clock control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXECKDIV : TXECKDIV
bits : 0 - 7 (8 bit)
access : read-write
TOCKDIV : TOCKDIV
bits : 8 - 15 (8 bit)
access : read-write
DSI Host timeout counter configuration register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPRD_TOCNT : LPRD_TOCNT
bits : 0 - 15 (16 bit)
access : read-write
DSI Host timeout counter configuration register 3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSWR_TOCNT : HSWR_TOCNT
bits : 0 - 15 (16 bit)
access : read-write
PM : PM
bits : 24 - 24 (1 bit)
access : read-write
DSI Host timeout counter configuration register 4
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPWR_TOCNT : LPWR_TOCNT
bits : 0 - 15 (16 bit)
access : read-write
DSI Host timeout counter configuration register 5
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTA_TOCNT : BTA_TOCNT
bits : 0 - 15 (16 bit)
access : read-write
DSI Host clock lane configuration register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPCC : DPCC
bits : 0 - 0 (1 bit)
access : read-write
ACR : ACR
bits : 1 - 1 (1 bit)
access : read-write
DSI Host clock lane timer configuration register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LP2HS_TIME : LP2HS_TIME
bits : 0 - 9 (10 bit)
access : read-write
HS2LP_TIME : HS2LP_TIME
bits : 16 - 25 (10 bit)
access : read-write
DSI Host data lane timer configuration register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LP2HS_TIME : LP2HS_TIME
bits : 0 - 9 (10 bit)
access : read-write
HS2LP_TIME : HS2LP_TIME
bits : 16 - 25 (10 bit)
access : read-write
DSI Host PHY control register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEN : DEN
bits : 1 - 1 (1 bit)
access : read-write
CKE : CKE
bits : 2 - 2 (1 bit)
access : read-write
DSI Host PHY configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NL : NL
bits : 0 - 1 (2 bit)
access : read-write
SW_TIME : SW_TIME
bits : 8 - 15 (8 bit)
access : read-write
DSI Host PHY ULPS control register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
URCL : URCL
bits : 0 - 0 (1 bit)
access : read-write
UECL : UECL
bits : 1 - 1 (1 bit)
access : read-write
URDL : URDL
bits : 2 - 2 (1 bit)
access : read-write
UEDL : UEDL
bits : 3 - 3 (1 bit)
access : read-write
DSI Host PHY TX triggers configuration register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_TRIG : TX_TRIG
bits : 0 - 3 (4 bit)
access : read-write
DSI Host PHY status register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PD : PD
bits : 1 - 1 (1 bit)
access : read-only
PSSC : PSSC
bits : 2 - 2 (1 bit)
access : read-only
UANC : UANC
bits : 3 - 3 (1 bit)
access : read-only
PSS0 : PSS0
bits : 4 - 4 (1 bit)
access : read-only
UAN0 : UAN0
bits : 5 - 5 (1 bit)
access : read-only
RUE0 : RUE0
bits : 6 - 6 (1 bit)
access : read-only
PSS1 : PSS1
bits : 7 - 7 (1 bit)
access : read-only
UAN1 : UAN1
bits : 8 - 8 (1 bit)
access : read-only
DSI Host interrupt and status register 0
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AE0 : AE0
bits : 0 - 0 (1 bit)
access : read-only
AE1 : AE1
bits : 1 - 1 (1 bit)
access : read-only
AE2 : AE2
bits : 2 - 2 (1 bit)
access : read-only
AE3 : AE3
bits : 3 - 3 (1 bit)
access : read-only
AE4 : AE4
bits : 4 - 4 (1 bit)
access : read-only
AE5 : AE5
bits : 5 - 5 (1 bit)
access : read-only
AE6 : AE6
bits : 6 - 6 (1 bit)
access : read-only
AE7 : AE7
bits : 7 - 7 (1 bit)
access : read-only
AE8 : AE8
bits : 8 - 8 (1 bit)
access : read-only
AE9 : AE9
bits : 9 - 9 (1 bit)
access : read-only
AE10 : AE10
bits : 10 - 10 (1 bit)
access : read-only
AE11 : AE11
bits : 11 - 11 (1 bit)
access : read-only
AE12 : AE12
bits : 12 - 12 (1 bit)
access : read-only
AE13 : AE13
bits : 13 - 13 (1 bit)
access : read-only
AE14 : AE14
bits : 14 - 14 (1 bit)
access : read-only
AE15 : AE15
bits : 15 - 15 (1 bit)
access : read-only
PE0 : PE0
bits : 16 - 16 (1 bit)
access : read-only
PE1 : PE1
bits : 17 - 17 (1 bit)
access : read-only
PE2 : PE2
bits : 18 - 18 (1 bit)
access : read-only
PE3 : PE3
bits : 19 - 19 (1 bit)
access : read-only
PE4 : PE4
bits : 20 - 20 (1 bit)
access : read-only
DSI Host LTDC VCID register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCID : VCID
bits : 0 - 1 (2 bit)
access : read-write
DSI Host interrupt and status register 1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOHSTX : TOHSTX
bits : 0 - 0 (1 bit)
access : read-only
TOLPRX : TOLPRX
bits : 1 - 1 (1 bit)
access : read-only
ECCSE : ECCSE
bits : 2 - 2 (1 bit)
access : read-only
ECCME : ECCME
bits : 3 - 3 (1 bit)
access : read-only
CRCE : CRCE
bits : 4 - 4 (1 bit)
access : read-only
PSE : PSE
bits : 5 - 5 (1 bit)
access : read-only
EOTPE : EOTPE
bits : 6 - 6 (1 bit)
access : read-only
LPWRE : LPWRE
bits : 7 - 7 (1 bit)
access : read-only
GCWRE : GCWRE
bits : 8 - 8 (1 bit)
access : read-only
GPWRE : GPWRE
bits : 9 - 9 (1 bit)
access : read-only
GPTXE : GPTXE
bits : 10 - 10 (1 bit)
access : read-only
GPRDE : GPRDE
bits : 11 - 11 (1 bit)
access : read-only
GPRXE : GPRXE
bits : 12 - 12 (1 bit)
access : read-only
DSI Host interrupt enable register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AE0IE : AE0IE
bits : 0 - 0 (1 bit)
access : read-write
AE1IE : AE1IE
bits : 1 - 1 (1 bit)
access : read-write
AE2IE : AE2IE
bits : 2 - 2 (1 bit)
access : read-write
AE3IE : AE3IE
bits : 3 - 3 (1 bit)
access : read-write
AE4IE : AE4IE
bits : 4 - 4 (1 bit)
access : read-write
AE5IE : AE5IE
bits : 5 - 5 (1 bit)
access : read-write
AE6IE : AE6IE
bits : 6 - 6 (1 bit)
access : read-write
AE7IE : AE7IE
bits : 7 - 7 (1 bit)
access : read-write
AE8IE : AE8IE
bits : 8 - 8 (1 bit)
access : read-write
AE9IE : AE9IE
bits : 9 - 9 (1 bit)
access : read-write
AE10IE : AE10IE
bits : 10 - 10 (1 bit)
access : read-write
AE11IE : AE11IE
bits : 11 - 11 (1 bit)
access : read-write
AE12IE : AE12IE
bits : 12 - 12 (1 bit)
access : read-write
AE13IE : AE13IE
bits : 13 - 13 (1 bit)
access : read-write
AE14IE : AE14IE
bits : 14 - 14 (1 bit)
access : read-write
AE15IE : AE15IE
bits : 15 - 15 (1 bit)
access : read-write
PE0IE : PE0IE
bits : 16 - 16 (1 bit)
access : read-write
PE1IE : PE1IE
bits : 17 - 17 (1 bit)
access : read-write
PE2IE : PE2IE
bits : 18 - 18 (1 bit)
access : read-write
PE3IE : PE3IE
bits : 19 - 19 (1 bit)
access : read-write
PE4IE : PE4IE
bits : 20 - 20 (1 bit)
access : read-write
DSI Host interrupt enable register 1
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOHSTXIE : TOHSTXIE
bits : 0 - 0 (1 bit)
access : read-write
TOLPRXIE : TOLPRXIE
bits : 1 - 1 (1 bit)
access : read-write
ECCSEIE : ECCSEIE
bits : 2 - 2 (1 bit)
access : read-write
ECCMEIE : ECCMEIE
bits : 3 - 3 (1 bit)
access : read-write
CRCEIE : CRCEIE
bits : 4 - 4 (1 bit)
access : read-write
PSEIE : PSEIE
bits : 5 - 5 (1 bit)
access : read-write
EOTPEIE : EOTPEIE
bits : 6 - 6 (1 bit)
access : read-write
LPWREIE : LPWREIE
bits : 7 - 7 (1 bit)
access : read-write
GCWREIE : GCWREIE
bits : 8 - 8 (1 bit)
access : read-write
GPWREIE : GPWREIE
bits : 9 - 9 (1 bit)
access : read-write
GPTXEIE : GPTXEIE
bits : 10 - 10 (1 bit)
access : read-write
GPRDEIE : GPRDEIE
bits : 11 - 11 (1 bit)
access : read-write
GPRXEIE : GPRXEIE
bits : 12 - 12 (1 bit)
access : read-write
DSI Host force interrupt register 0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAE0 : FAE0
bits : 0 - 0 (1 bit)
access : write-only
FAE1 : FAE1
bits : 1 - 1 (1 bit)
access : write-only
FAE2 : FAE2
bits : 2 - 2 (1 bit)
access : write-only
FAE3 : FAE3
bits : 3 - 3 (1 bit)
access : write-only
FAE4 : FAE4
bits : 4 - 4 (1 bit)
access : write-only
FAE5 : FAE5
bits : 5 - 5 (1 bit)
access : write-only
FAE6 : FAE6
bits : 6 - 6 (1 bit)
access : write-only
FAE7 : FAE7
bits : 7 - 7 (1 bit)
access : write-only
FAE8 : FAE8
bits : 8 - 8 (1 bit)
access : write-only
FAE9 : FAE9
bits : 9 - 9 (1 bit)
access : write-only
FAE10 : FAE10
bits : 10 - 10 (1 bit)
access : write-only
FAE11 : FAE11
bits : 11 - 11 (1 bit)
access : write-only
FAE12 : FAE12
bits : 12 - 12 (1 bit)
access : write-only
FAE13 : FAE13
bits : 13 - 13 (1 bit)
access : write-only
FAE14 : FAE14
bits : 14 - 14 (1 bit)
access : write-only
FAE15 : FAE15
bits : 15 - 15 (1 bit)
access : write-only
FPE0 : FPE0
bits : 16 - 16 (1 bit)
access : write-only
FPE1 : FPE1
bits : 17 - 17 (1 bit)
access : write-only
FPE2 : FPE2
bits : 18 - 18 (1 bit)
access : write-only
FPE3 : FPE3
bits : 19 - 19 (1 bit)
access : write-only
FPE4 : FPE4
bits : 20 - 20 (1 bit)
access : write-only
DSI Host force interrupt register 1
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTOHSTX : FTOHSTX
bits : 0 - 0 (1 bit)
access : write-only
FTOLPRX : FTOLPRX
bits : 1 - 1 (1 bit)
access : write-only
FECCSE : FECCSE
bits : 2 - 2 (1 bit)
access : write-only
FECCME : FECCME
bits : 3 - 3 (1 bit)
access : write-only
FCRCE : FCRCE
bits : 4 - 4 (1 bit)
access : write-only
FPSE : FPSE
bits : 5 - 5 (1 bit)
access : write-only
FEOTPE : FEOTPE
bits : 6 - 6 (1 bit)
access : write-only
FLPWRE : FLPWRE
bits : 7 - 7 (1 bit)
access : write-only
FGCWRE : FGCWRE
bits : 8 - 8 (1 bit)
access : write-only
FGPWRE : FGPWRE
bits : 9 - 9 (1 bit)
access : write-only
FGPTXE : FGPTXE
bits : 10 - 10 (1 bit)
access : write-only
FGPRDE : FGPRDE
bits : 11 - 11 (1 bit)
access : write-only
FGPRXE : FGPRXE
bits : 12 - 12 (1 bit)
access : write-only
DSI Host data lane timer read configuration register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRD_TIME : MRD_TIME
bits : 0 - 14 (15 bit)
access : read-write
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