\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
TIM6/TIM7 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : CEN
bits : 0 - 0 (1 bit)
access : read-write
UDIS : UDIS
bits : 1 - 1 (1 bit)
access : read-write
URS : URS
bits : 2 - 2 (1 bit)
access : read-write
OPM : OPM
bits : 3 - 3 (1 bit)
access : read-write
ARPE : ARPE
bits : 7 - 7 (1 bit)
access : read-write
UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)
access : read-write
TIM6/TIM7 status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : UIF
bits : 0 - 0 (1 bit)
access : read-write
TIM6/TIM7 event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UG : UG
bits : 0 - 0 (1 bit)
access : read-write
TIM6/TIM7 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 15 (16 bit)
access : read-write
UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
access : read-only
prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value
bits : 0 - 15 (16 bit)
auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : Low Auto-reload value
bits : 0 - 15 (16 bit)
TIM6/TIM7 control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMS : MMS
bits : 4 - 6 (3 bit)
access : read-write
TIM6/TIM7 DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : UIE
bits : 0 - 0 (1 bit)
access : read-write
UDE : UDE
bits : 8 - 8 (1 bit)
access : read-only
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