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TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TIMx_CR1

TIMx_SR

TIMx_EGR

TIMx_CCMR1_Output

TIMx_CCMR1_Input

TIMx_CCER

TIMx_CNT

TIMx_PSC

TIMx_ARR

TIMx_CCR1

TIMx_CCR2

TIMx_TISEL

TIMx_SMCR

TIMx_DIER


TIMx_CR1

TIM12 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CR1 TIMx_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM ARPE CKD UIFREMAP

CEN : CEN
bits : 0 - 0 (1 bit)
access : read-write

UDIS : UDIS
bits : 1 - 1 (1 bit)
access : read-write

URS : URS
bits : 2 - 2 (1 bit)
access : read-write

OPM : OPM
bits : 3 - 3 (1 bit)
access : read-write

ARPE : ARPE
bits : 7 - 7 (1 bit)
access : read-write

CKD : CKD
bits : 8 - 9 (2 bit)
access : read-write

UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)
access : read-write


TIMx_SR

TIM12 status register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_SR TIMx_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC2IF TIF CC1OF CC2OF

UIF : UIF
bits : 0 - 0 (1 bit)
access : read-write

CC1IF : CC1IF
bits : 1 - 1 (1 bit)
access : read-write

CC2IF : CC2IF
bits : 2 - 2 (1 bit)
access : read-write

TIF : TIF
bits : 6 - 6 (1 bit)
access : read-write

CC1OF : CC1OF
bits : 9 - 9 (1 bit)
access : read-write

CC2OF : CC2OF
bits : 10 - 10 (1 bit)
access : read-write


TIMx_EGR

event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TIMx_EGR TIMx_EGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G CC2G TG

UG : Update generation
bits : 0 - 0 (1 bit)

CC1G : Capture/compare 1 generation
bits : 1 - 1 (1 bit)

CC2G : Capture/compare 2 generation
bits : 2 - 2 (1 bit)

TG : Trigger generation
bits : 6 - 6 (1 bit)


TIMx_CCMR1_Output

capture/compare mode register 1 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CCMR1_Output TIMx_CCMR1_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S OC1FE OC1PE OC1M OC1CE CC2S OC2FE OC2PE OC2M OC2CE OC1M_3 OC2M_3

CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)

OC1FE : Output compare 1 fast enable
bits : 2 - 2 (1 bit)

OC1PE : Output compare 1 preload enable
bits : 3 - 3 (1 bit)

OC1M : Output compare 1 mode
bits : 4 - 6 (3 bit)

OC1CE : Output compare 1 clear enable
bits : 7 - 7 (1 bit)

CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)

OC2FE : Output compare 2 fast enable
bits : 10 - 10 (1 bit)

OC2PE : Output compare 2 preload enable
bits : 11 - 11 (1 bit)

OC2M : Output compare 2 mode
bits : 12 - 14 (3 bit)

OC2CE : Output compare 2 clear enable
bits : 15 - 15 (1 bit)

OC1M_3 : Output Compare 1 mode - bit 3
bits : 16 - 16 (1 bit)

OC2M_3 : Output Compare 2 mode - bit 3
bits : 24 - 24 (1 bit)


TIMx_CCMR1_Input

capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIMx_CCMR1_Output
reset_Mask : 0x0

TIMx_CCMR1_Input TIMx_CCMR1_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S IC1PSC IC1F CC2S IC2PSC IC2F

CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)

IC1PSC : Input capture 1 prescaler
bits : 2 - 3 (2 bit)

IC1F : Input capture 1 filter
bits : 4 - 7 (4 bit)

CC2S : Capture/compare 2 selection
bits : 8 - 9 (2 bit)

IC2PSC : Input capture 2 prescaler
bits : 10 - 11 (2 bit)

IC2F : Input capture 2 filter
bits : 12 - 15 (4 bit)


TIMx_CCER

TIM12 capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CCER TIMx_CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NP CC2E CC2P CC2NP

CC1E : CC1E
bits : 0 - 0 (1 bit)
access : read-write

CC1P : CC1P
bits : 1 - 1 (1 bit)
access : read-write

CC1NP : CC1NP
bits : 3 - 3 (1 bit)
access : read-write

CC2E : CC2E
bits : 4 - 4 (1 bit)
access : read-write

CC2P : CC2P
bits : 5 - 5 (1 bit)
access : read-write

CC2NP : CC2NP
bits : 7 - 7 (1 bit)
access : read-write


TIMx_CNT

TIM12 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CNT TIMx_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT UIFCPY

CNT : CNT
bits : 0 - 15 (16 bit)
access : read-write

UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
access : read-write


TIMx_PSC

TIM12 prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_PSC TIMx_PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : PSC
bits : 0 - 15 (16 bit)
access : read-write


TIMx_ARR

TIM12 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_ARR TIMx_ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ARR
bits : 0 - 15 (16 bit)
access : read-write


TIMx_CCR1

TIM12 capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CCR1 TIMx_CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : CCR1
bits : 0 - 15 (16 bit)
access : read-write


TIMx_CCR2

TIM12 capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CCR2 TIMx_CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2

CCR2 : CCR2
bits : 0 - 15 (16 bit)
access : read-write


TIMx_TISEL

TIMx timer input selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_TISEL TIMx_TISEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI1SEL TI2SEL

TI1SEL : TI1SEL
bits : 0 - 3 (4 bit)
access : read-write

TI2SEL : TI2SEL
bits : 8 - 11 (4 bit)
access : read-write


TIMx_SMCR

slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_SMCR TIMx_SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS TS MSM SMS_3 TS_4_3

SMS : Slave mode selection
bits : 0 - 2 (3 bit)

TS : Trigger selection
bits : 4 - 6 (3 bit)

MSM : Master/Slave mode
bits : 7 - 7 (1 bit)

SMS_3 : Slave mode selection - bit 3
bits : 16 - 16 (1 bit)

TS_4_3 : Trigger selection
bits : 20 - 21 (2 bit)


TIMx_DIER

TIM12 Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_DIER TIMx_DIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE CC2IE TIE

UIE : UIE
bits : 0 - 0 (1 bit)
access : read-write

CC1IE : CC1IE
bits : 1 - 1 (1 bit)
access : read-write

CC2IE : CC2IE
bits : 2 - 2 (1 bit)
access : read-write

TIE : TIE
bits : 6 - 6 (1 bit)
access : read-write



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