\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
power control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPDS : Low-power deep sleep
bits : 0 - 0 (1 bit)
PDDS : Power down deepsleep
bits : 1 - 1 (1 bit)
CWUF : Clear wakeup flag
bits : 2 - 2 (1 bit)
CSBF : Clear standby flag
bits : 3 - 3 (1 bit)
PVDE : Power voltage detector enable
bits : 4 - 4 (1 bit)
PLS : PVD level selection
bits : 5 - 7 (3 bit)
DBP : Disable backup domain write protection
bits : 8 - 8 (1 bit)
FPDS : Flash power down in Stop mode
bits : 9 - 9 (1 bit)
power control/status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUF : Wakeup flag
bits : 0 - 0 (1 bit)
access : read-only
SBF : Standby flag
bits : 1 - 1 (1 bit)
access : read-only
PVDO : PVD output
bits : 2 - 2 (1 bit)
access : read-only
BRR : Backup regulator ready
bits : 3 - 3 (1 bit)
access : read-only
EWUP : Enable WKUP pin
bits : 8 - 8 (1 bit)
access : read-write
BRE : Backup regulator enable
bits : 9 - 9 (1 bit)
access : read-write
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