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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

Registers

STATUS

CHNLSWREQUEST

CHNLUSEBURSTSET

CHNLUSEBURSTCLR

CHNLREQMASKSET

CHNLREQMASKCLR

CHNLENABLESET

CHNLENABLECLR

CHNLPRIALTSET

CHNLPRIALTCLR

CHNLPRIORITYSET

CHNLPRIORITYCLR

CFG

ERRCLR

CTRLBASEPTR

ALTCTRLBASEPTR


STATUS

DMA Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTER_ENABLE

MASTER_ENABLE : MASTER_ENABLE
bits : 0 - 0 (1 bit)
access : read-only


CHNLSWREQUEST

DMA Channel Software Request Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHNLSWREQUEST CHNLSWREQUEST write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_SW_REQUEST

CHNL_SW_REQUEST : CHNL_SW_REQUEST
bits : 0 - 31 (32 bit)
access : write-only


CHNLUSEBURSTSET

DMA Channel Useburst Set Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNLUSEBURSTSET CHNLUSEBURSTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_USEBURST_SET

CHNL_USEBURST_SET : CHNL_USEBURST_SET
bits : 0 - 31 (32 bit)
access : read-write


CHNLUSEBURSTCLR

DMA Channel Useburst Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHNLUSEBURSTCLR CHNLUSEBURSTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_USEBURST_CLR

CHNL_USEBURST_CLR : CHNL_USEBURST_CLR
bits : 0 - 31 (32 bit)
access : write-only


CHNLREQMASKSET

DMA Channel Request Mask Set Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNLREQMASKSET CHNLREQMASKSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_REQ_MASK_SET

CHNL_REQ_MASK_SET : CHNL_REQ_MASK_SET
bits : 0 - 31 (32 bit)
access : read-write


CHNLREQMASKCLR

DMA Channel Request Mask Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHNLREQMASKCLR CHNLREQMASKCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_REQ_MASK_CLR

CHNL_REQ_MASK_CLR : CHNL_REQ_MASK_CLR
bits : 0 - 31 (32 bit)
access : write-only


CHNLENABLESET

DMA Channel Enable Set Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNLENABLESET CHNLENABLESET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE_SET

CHNL_ENABLE_SET : CHNL_ENABLE_SET
bits : 0 - 31 (32 bit)
access : read-write


CHNLENABLECLR

DMA Channel Enable Clear Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHNLENABLECLR CHNLENABLECLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE_CLR

CHNL_ENABLE_CLR : CHNL_ENABLE_CLR
bits : 0 - 31 (32 bit)
access : write-only


CHNLPRIALTSET

DMA Channel Primary-Alternate Set Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNLPRIALTSET CHNLPRIALTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_PRI_ALT_SET

CHNL_PRI_ALT_SET : CHNL_PRI_ALT_SET
bits : 0 - 31 (32 bit)
access : read-write


CHNLPRIALTCLR

DMA Channel Primary-Alternate Clear Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHNLPRIALTCLR CHNLPRIALTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_PRI_ALT_CLR

CHNL_PRI_ALT_CLR : CHNL_PRI_ALT_CLR
bits : 0 - 31 (32 bit)
access : write-only


CHNLPRIORITYSET

DMA Channel Priority Set Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNLPRIORITYSET CHNLPRIORITYSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_PRIORITY_SET

CHNL_PRIORITY_SET : CHNL_PRIORITY_SET
bits : 0 - 31 (32 bit)
access : read-write


CHNLPRIORITYCLR

DMA Channel Priority Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHNLPRIORITYCLR CHNLPRIORITYCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_PRIORITY_CLR

CHNL_PRIORITY_CLR : CHNL_PRIORITY_CLR
bits : 0 - 31 (32 bit)
access : write-only


CFG

DMA Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CFG CFG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTER_ENABLE

MASTER_ENABLE : MASTER_ENABLE
bits : 0 - 0 (1 bit)
access : write-only


ERRCLR

DMA Bus Error Clear Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERRCLR ERRCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_CLR

ERR_CLR : ERR_CLR
bits : 0 - 0 (1 bit)
access : read-write


CTRLBASEPTR

DMA Control Data Base Pointer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLBASEPTR CTRLBASEPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL_BASE_PTR

CTRL_BASE_PTR : CTRL_BASE_PTR
bits : 10 - 31 (22 bit)
access : read-write


ALTCTRLBASEPTR

DMA Channel Alternate Control Data Base Pointer Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ALTCTRLBASEPTR ALTCTRLBASEPTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALT_CTRL_BASE_PTR

ALT_CTRL_BASE_PTR : ALT_CTRL_BASE_PTR
bits : 0 - 31 (32 bit)
access : read-only



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