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SBI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR0

CR2

SR

BR0

CR1

DBR

I2CAR


CR0

SBI Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBIEN

SBIEN : SBIEN
bits : 7 - 7 (1 bit)
access : read-write


CR2

SBI Control Register 2 (I2C Mode)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST SBIM PIN BB TRX MST

SWRST : SWRST
bits : 0 - 1 (2 bit)
access : write-only

SBIM : SBIM
bits : 2 - 3 (2 bit)
access : write-only

PIN : PIN
bits : 4 - 4 (1 bit)
access : write-only

BB : BB
bits : 5 - 5 (1 bit)
access : write-only

TRX : TRX
bits : 6 - 6 (1 bit)
access : write-only

MST : MST
bits : 7 - 7 (1 bit)
access : write-only


SR

SBI Status Register (I2C Mode)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LRB ADO AAS AL PIN BB TRX MST

LRB : LRB
bits : 0 - 0 (1 bit)
access : read-only

ADO : ADO
bits : 1 - 1 (1 bit)
access : read-only

AAS : AAS
bits : 2 - 2 (1 bit)
access : read-only

AL : AL
bits : 3 - 3 (1 bit)
access : read-only

PIN : PIN
bits : 4 - 4 (1 bit)
access : read-only

BB : BB
bits : 5 - 5 (1 bit)
access : read-only

TRX : TRX
bits : 6 - 6 (1 bit)
access : read-only

MST : MST
bits : 7 - 7 (1 bit)
access : read-only


BR0

SBI Baud Rate Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR0 BR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2SBI

I2SBI : I2SBI
bits : 6 - 6 (1 bit)
access : read-write


CR1

SBI Control Register 1 (I2C Mode)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRMON SCK ACK BC

SWRMON : SWRMON
bits : 0 - 0 (1 bit)
access : read-only

SCK : SCK
bits : 0 - 2 (3 bit)
access : write-only

ACK : ACK
bits : 4 - 4 (1 bit)
access : read-write

BC : BC
bits : 5 - 7 (3 bit)
access : read-write


DBR

SBI Data Buffer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBR DBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB

DB : DB
bits : 0 - 7 (8 bit)
access : read-write


I2CAR

SBI I2C Bus Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CAR I2CAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALS SA

ALS : ALS
bits : 0 - 0 (1 bit)
access : read-write

SA : SA
bits : 1 - 7 (7 bit)
access : read-write



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