\n

VE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x98 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0xDC Bytes (0x0)
size : 0x98 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x174 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x178 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x17C Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x19C Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EN

REPTIME

VQ1

CIDKI1

CIDKP1

CIQKI1

CIQKP1

VDIH1

VDILH1

VQIH1

VQILH1

FPWMCHG1

MDPRD1

MINPLS1

TRGCRC1

VDCL1

COS1

SIN1

TRGMODE

COSM1

SINM1

SECTOR1

SECTORM1

IAO1

IBO1

ICO1

IAADC1

IBADC1

ICADC1

VDC1

ID1

IQ1

TADC

ERRINTEN

CMPU1

CMPV1

CMPW1

OUTCR1

TRGCMP01

TRGCMP11

TRGSEL1

EMGRS1

COMPEND

ERRDET

SCHTASKRUN

TMPREG0

TMPREG1

TMPREG2

TMPREG3

TMPREG4

CPURUNTRG

TMPREG5

TASKAPP

ACTSCH

MCTLF1

MODE1

FMODE1

TPWM1

OMEGA1

THETA1

IDREF1

IQREF1

VD1


EN

VE enable_disable
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VEEN VEIDLEN

VEEN : VEEN
bits : 0 - 0 (1 bit)
access : read-write

VEIDLEN : VEIDLEN
bits : 1 - 1 (1 bit)
access : read-write


REPTIME

Schedule repeat count
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REPTIME REPTIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREPB

VREPB : VREPB
bits : 4 - 7 (4 bit)
access : read-write


VQ1

q-axis voltage (voltage _V_ _ maximum voltage * 2^31)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VQ1 VQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VQ

VQ : VQ
bits : 0 - 31 (32 bit)
access : read-write


CIDKI1

Integral coefficient for PI control of d-axis
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIDKI1 CIDKI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIDKI

CIDKI : CIDKI
bits : 0 - 15 (16 bit)
access : read-write


CIDKP1

Proportional coefficient for PI control of d-axis
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIDKP1 CIDKP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIDKP

CIDKP : CIDKP
bits : 0 - 15 (16 bit)
access : read-write


CIQKI1

Integral coefficient for PI control of q-axis
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIQKI1 CIQKI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIQKI

CIQKI : CIQKI
bits : 0 - 15 (16 bit)
access : read-write


CIQKP1

Proportional coefficient for PI control of q-axis
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIQKP1 CIQKP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIQKP

CIQKP : CIQKP
bits : 0 - 15 (16 bit)
access : read-write


VDIH1

Upper 32 bits of integral term (VDI) of d-axis voltage
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDIH1 VDIH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDIH

VDIH : VDIH
bits : 0 - 31 (32 bit)
access : read-write


VDILH1

Lower 32 bits of integral term (VDI) of d-axis voltage
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDILH1 VDILH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDILH

VDILH : VDILH
bits : 16 - 31 (16 bit)
access : read-write


VQIH1

Upper 32 bits of integral term (VQI) of q-axis voltage
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VQIH1 VQIH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VQIH

VQIH : VQIH
bits : 0 - 31 (32 bit)
access : read-write


VQILH1

Lower 32 bits of integral term (VQI) of q-axis voltage
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VQILH1 VQILH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VQILH

VQILH : VQILH
bits : 16 - 31 (16 bit)
access : read-write


FPWMCHG1

Switching speed (for 2-phase modulation and shift PWM)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPWMCHG1 FPWMCHG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPWMCHG

FPWMCHG : FPWMCHG
bits : 0 - 15 (16 bit)
access : read-write


MDPRD1

PWM period (to be set identically with PMD's PWM period)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDPRD1 MDPRD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMDPRD

VMDPRD : VMDPRD
bits : 0 - 15 (16 bit)
access : read-write


MINPLS1

Minimum pulse width
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MINPLS1 MINPLS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINPLS

MINPLS : MINPLS
bits : 0 - 15 (16 bit)
access : read-write


TRGCRC1

Synchronizing trigger correction value
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGCRC1 TRGCRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGCRC

TRGCRC : TRGCRC
bits : 0 - 15 (16 bit)
access : read-write


VDCL1

Cosine value at THETA for output conversion (Q15 data)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDCL1 VDCL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDCL

VDCL : VDCL
bits : 0 - 15 (16 bit)
access : read-write


COS1

Cosine value at THETA for output conversion (Q15 data)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COS1 COS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COS

COS : COS
bits : 0 - 15 (16 bit)
access : read-write


SIN1

Sine value at THETA for output conversion (Q15 data)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIN1 SIN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIN

SIN : SIN
bits : 0 - 15 (16 bit)
access : read-write


TRGMODE

Start trigger mode
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMODE TRGMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTRGB

VTRGB : VTRGB
bits : 2 - 3 (2 bit)
access : read-write


COSM1

Previous cosine value for input processing (Q15 data)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COSM1 COSM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COSM

COSM : COSM
bits : 0 - 15 (16 bit)
access : read-write


SINM1

Previous sine value for input processing (Q15 data)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SINM1 SINM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SINM

SINM : SINM
bits : 0 - 15 (16 bit)
access : read-write


SECTOR1

Sector information (0-11)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECTOR1 SECTOR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECTOR

SECTOR : SECTOR
bits : 0 - 3 (4 bit)
access : read-write


SECTORM1

Previous sector information for input processing (0-11)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECTORM1 SECTORM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECTORM

SECTORM : SECTORM
bits : 0 - 3 (4 bit)
access : read-write


IAO1

AD conversion result of a-phase zero-current
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IAO1 IAO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IAO

IAO : IAO
bits : 0 - 15 (16 bit)
access : read-write


IBO1

AD conversion result of b-phase zero-current
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IBO1 IBO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB0

IB0 : IB0
bits : 0 - 15 (16 bit)
access : read-write


ICO1

AD conversion result of c-phase zero-current
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICO1 ICO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC0

IC0 : IC0
bits : 0 - 15 (16 bit)
access : read-write


IAADC1

AD conversion result of a-phase current
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IAADC1 IAADC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IAADC

IAADC : IAADC
bits : 0 - 15 (16 bit)
access : read-write


IBADC1

AD conversion result of b-phase current
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IBADC1 IBADC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IBADC

IBADC : IBADC
bits : 0 - 15 (16 bit)
access : read-write


ICADC1

AD conversion result of c-phase current
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICADC1 ICADC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICADC

ICADC : ICADC
bits : 0 - 15 (16 bit)
access : read-write


VDC1

DC supply voltage (voltage _V_ _ maximum voltage * 2^15)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDC1 VDC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDC

VDC : VDC
bits : 0 - 15 (16 bit)
access : read-write


ID1

d-axis current (current _A_ _ maximum current * 2^31)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID1 ID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)
access : read-write


IQ1

q-axis current (current _A_ _ maximum current * 2^31)
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IQ1 IQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IQ

IQ : IQ
bits : 0 - 31 (32 bit)
access : read-write


TADC

ADC start wait setting
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TADC TADC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TADC

TADC : TADC
bits : 0 - 15 (16 bit)
access : read-write


ERRINTEN

Error interrupt enable_disable
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERRINTEN ERRINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERRENB

VERRENB : VERRENB
bits : 1 - 1 (1 bit)
access : read-write


CMPU1

PMD control_ CMPU setting
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPU1 CMPU1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCMPU

VCMPU : VCMPU
bits : 0 - 15 (16 bit)
access : read-write


CMPV1

PMD control_ CMPV setting
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV1 CMPV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCMPV

VCMPV : VCMPV
bits : 0 - 15 (16 bit)
access : read-write


CMPW1

PMD control_ CMPW setting
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPW1 CMPW1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCMPW

VCMPW : VCMPW
bits : 0 - 15 (16 bit)
access : read-write


OUTCR1

PMD control_ Output control (MDOUT)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCR1 OUTCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U0C VOC W0C UPWM VPWM WPWM

U0C : U0C
bits : 0 - 1 (2 bit)
access : read-write

VOC : VOC
bits : 2 - 3 (2 bit)
access : read-write

W0C : W0C
bits : 4 - 5 (2 bit)
access : read-write

UPWM : UPWM
bits : 6 - 6 (1 bit)
access : read-write

VPWM : VPWM
bits : 7 - 7 (1 bit)
access : read-write

WPWM : WPWM
bits : 8 - 8 (1 bit)
access : read-write


TRGCMP01

PMD control_ TRGCMP0 setting
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGCMP01 TRGCMP01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTRGCMP0

VTRGCMP0 : VTRGCMP0
bits : 0 - 15 (16 bit)
access : read-write


TRGCMP11

PMD control_ TRGCMP1 setting
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGCMP11 TRGCMP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTRGCMP1

VTRGCMP1 : VTRGCMP1
bits : 0 - 15 (16 bit)
access : read-write


TRGSEL1

PMD control_ Trigger selection
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSEL1 TRGSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTRGSEL

VTRGSEL : VTRGSEL
bits : 0 - 2 (3 bit)
access : read-write


EMGRS1

PMD control_ EMG return (EMGCR_EMGRS_)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMGRS1 EMGRS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMGRS

EMGRS : EMGRS
bits : 0 - 0 (1 bit)
access : read-write


COMPEND

VE forced termination
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

COMPEND COMPEND write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCENDB

VCENDB : VCENDB
bits : 1 - 1 (1 bit)
access : write-only


ERRDET

Error detection
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERRDET ERRDET read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERRDB

VERRDB : VERRDB
bits : 1 - 1 (1 bit)
access : read-only


SCHTASKRUN

Schedule executing flag_executing task
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCHTASKRUN SCHTASKRUN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRSCHB VRTASKB

VRSCHB : VRSCHB
bits : 5 - 5 (1 bit)
access : read-only

VRTASKB : VRTASKB
bits : 6 - 9 (4 bit)
access : read-only


TMPREG0

Temporary register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPREG0 TMPREG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMPREG0

TMPREG0 : TMPREG0
bits : 0 - 31 (32 bit)
access : read-write


TMPREG1

Temporary register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPREG1 TMPREG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMPREG1

TMPREG1 : TMPREG1
bits : 0 - 31 (32 bit)
access : read-write


TMPREG2

Temporary register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPREG2 TMPREG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMPREG2

TMPREG2 : TMPREG2
bits : 0 - 31 (32 bit)
access : read-write


TMPREG3

Temporary register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPREG3 TMPREG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMPREG3

TMPREG3 : TMPREG3
bits : 0 - 31 (32 bit)
access : read-write


TMPREG4

Temporary register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPREG4 TMPREG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMPREG4

TMPREG4 : TMPREG4
bits : 0 - 31 (32 bit)
access : read-write


CPURUNTRG

CPU start trigger selection
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPURUNTRG CPURUNTRG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCPURTB

VCPURTB : VCPURTB
bits : 1 - 1 (1 bit)
access : write-only


TMPREG5

Temporary register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPREG5 TMPREG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMPREG5

TMPREG5 : TMPREG5
bits : 0 - 31 (32 bit)
access : read-write


TASKAPP

Task selection
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TASKAPP TASKAPP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTASKB

VTASKB : VTASKB
bits : 4 - 7 (4 bit)
access : read-write


ACTSCH

Operation schedule selection
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTSCH ACTSCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VACTB

VACTB : VACTB
bits : 4 - 7 (4 bit)
access : read-write


MCTLF1

Status flags
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTLF1 MCTLF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAVF LAVFM LVTF PLSLF PLSLFM

LAVF : LAVF
bits : 0 - 0 (1 bit)
access : read-write

LAVFM : LAVFM
bits : 1 - 1 (1 bit)
access : read-write

LVTF : LVTF
bits : 2 - 2 (1 bit)
access : read-write

PLSLF : PLSLF
bits : 4 - 4 (1 bit)
access : read-write

PLSLFM : PLSLFM
bits : 5 - 5 (1 bit)
access : read-write


MODE1

Task control mode
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PVIEN ZIEN OCRMD VDCSEL T4ATANEN T7SQRTEN

PVIEN : PVIEN
bits : 0 - 0 (1 bit)
access : read-write

ZIEN : ZIEN
bits : 1 - 1 (1 bit)
access : read-write

OCRMD : OCRMD
bits : 2 - 3 (2 bit)
access : read-write

VDCSEL : VDCSEL
bits : 4 - 4 (1 bit)
access : read-write

T4ATANEN : T4ATANEN
bits : 6 - 6 (1 bit)
access : read-write

T7SQRTEN : T7SQRTEN
bits : 7 - 7 (1 bit)
access : read-write


FMODE1

Flow control
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMODE1 FMODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C2PEN SPWMEN IDMODE IDPLMD CRCEN MREGDIS PIGSEL PHCVDIS SPWMMD

C2PEN : C2PEN
bits : 0 - 0 (1 bit)
access : read-write

SPWMEN : SPWMEN
bits : 1 - 1 (1 bit)
access : read-write

IDMODE : IDMODE
bits : 2 - 3 (2 bit)
access : read-write

IDPLMD : IDPLMD
bits : 5 - 5 (1 bit)
access : read-write

CRCEN : CRCEN
bits : 8 - 8 (1 bit)
access : read-write

MREGDIS : MREGDIS
bits : 9 - 9 (1 bit)
access : read-write

PIGSEL : PIGSEL
bits : 11 - 11 (1 bit)
access : read-write

PHCVDIS : PHCVDIS
bits : 12 - 12 (1 bit)
access : read-write

SPWMMD : SPWMMD
bits : 14 - 15 (2 bit)
access : read-write


TPWM1

PWM period rate (PWM period _s_* maximum speed * 2^16) setting
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPWM1 TPWM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPWM

TPWM : TPWM
bits : 0 - 15 (16 bit)
access : read-write


OMEGA1

Rotation speed (speed _Hz_ _ maximum speed * 2^15) setting
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMEGA1 OMEGA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OMEGA

OMEGA : OMEGA
bits : 0 - 15 (16 bit)
access : read-write


THETA1

Motor phase (motor phase _deg_ _ 360 * 2^16) setting
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THETA1 THETA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THETA

THETA : THETA
bits : 0 - 15 (16 bit)
access : read-write


IDREF1

d-axis reference value (current _A_ _ maximum current * 2^15)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDREF1 IDREF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDREF

IDREF : IDREF
bits : 0 - 15 (16 bit)
access : read-write


IQREF1

q-axis reference value (current _A_ _ maximum current * 2^15)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IQREF1 IQREF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IQREF

IQREF : IQREF
bits : 0 - 15 (16 bit)
access : read-write


VD1

d-axis voltage (voltage _V_ _ maximum voltage * 2^31)
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VD1 VD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VD

VD : VD
bits : 0 - 31 (32 bit)
access : read-write



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