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AD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x68 Bytes (0x0)
size : 0x70 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK

CMPCR0

CMPCR1

CMP0

CMP1

REG0

REG1

REG2

REG3

REG4

REG5

REG6

REG7

MOD0

REG8

REG9

REG10

REG11

PSEL6

PSEL7

PSEL8

PSEL9

PSEL10

PSEL11

MOD1

PINTS0

PINTS1

PINTS2

PINTS3

PINTS4

PINTS5

PSET0

PSET1

PSET2

PSET3

PSET4

PSET5

TSET03

TSET47

TSET811

SSET03

MOD2

SSET47

SSET811

ASET03

ASET47

ASET811

MOD3


CLK

AD Conversion Clock Setting Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCLK TSH

ADCLK : ADCLK
bits : 0 - 2 (3 bit)
access : read-write

TSH : TSH
bits : 3 - 6 (4 bit)
access : read-write


CMPCR0

AD Monitoring Setting Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCR0 CMPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGS0 ADBIG0 CMP0EN CMPCNT0

REGS0 : REGS0
bits : 0 - 3 (4 bit)
access : read-write

ADBIG0 : ADBIG0
bits : 4 - 4 (1 bit)
access : read-write

CMP0EN : CMP0EN
bits : 7 - 7 (1 bit)
access : read-write

CMPCNT0 : CMPCNT0
bits : 8 - 11 (4 bit)
access : read-write


CMPCR1

AD Monitoring Setting Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCR1 CMPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGS1 ADBIG1 CMP1EN CMPCNT1

REGS1 : REGS1
bits : 0 - 3 (4 bit)
access : read-write

ADBIG1 : ADBIG1
bits : 4 - 4 (1 bit)
access : read-write

CMP1EN : CMP1EN
bits : 7 - 7 (1 bit)
access : read-write

CMPCNT1 : CMPCNT1
bits : 8 - 11 (4 bit)
access : read-write


CMP0

AD Conversion Result Compare Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP0 CMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0CMP0

AD0CMP0 : AD0CMP0
bits : 4 - 15 (12 bit)
access : read-write


CMP1

AD Conversion Result Compare Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP1 CMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0CMP1

AD0CMP1 : AD0CMP1
bits : 4 - 15 (12 bit)
access : read-write


REG0

AD Conversion Result Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG0 REG0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR0RF OVR0 ADR00

ADR0RF : ADR0RF
bits : 0 - 0 (1 bit)
access : read-only

OVR0 : OVR0
bits : 1 - 1 (1 bit)
access : read-only

ADR00 : ADR00
bits : 4 - 15 (12 bit)
access : read-only


REG1

AD Conversion Result Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG1 REG1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR1RF OVR1 ADR10

ADR1RF : ADR1RF
bits : 0 - 0 (1 bit)
access : read-only

OVR1 : OVR1
bits : 1 - 1 (1 bit)
access : read-only

ADR10 : ADR10
bits : 4 - 15 (12 bit)
access : read-only


REG2

AD Conversion Result Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG2 REG2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR2RF OVR2 ADR20

ADR2RF : ADR2RF
bits : 0 - 0 (1 bit)
access : read-only

OVR2 : OVR2
bits : 1 - 1 (1 bit)
access : read-only

ADR20 : ADR20
bits : 4 - 15 (12 bit)
access : read-only


REG3

AD Conversion Result Register 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG3 REG3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR3RF OVR3 ADR30

ADR3RF : ADR3RF
bits : 0 - 0 (1 bit)
access : read-only

OVR3 : OVR3
bits : 1 - 1 (1 bit)
access : read-only

ADR30 : ADR30
bits : 4 - 15 (12 bit)
access : read-only


REG4

AD Conversion Result Register 4
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG4 REG4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR4RF OVR4 ADR40

ADR4RF : ADR4RF
bits : 0 - 0 (1 bit)
access : read-only

OVR4 : OVR4
bits : 1 - 1 (1 bit)
access : read-only

ADR40 : ADR40
bits : 4 - 15 (12 bit)
access : read-only


REG5

AD Conversion Result Register 5
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG5 REG5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR5RF OVR5 ADR50

ADR5RF : ADR5RF
bits : 0 - 0 (1 bit)
access : read-only

OVR5 : OVR5
bits : 1 - 1 (1 bit)
access : read-only

ADR50 : ADR50
bits : 4 - 15 (12 bit)
access : read-only


REG6

AD Conversion Result Register 6
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG6 REG6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR6RF OVR6 ADR60

ADR6RF : ADR6RF
bits : 0 - 0 (1 bit)
access : read-only

OVR6 : OVR6
bits : 1 - 1 (1 bit)
access : read-only

ADR60 : ADR60
bits : 4 - 15 (12 bit)
access : read-only


REG7

AD Conversion Result Register 7
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG7 REG7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR7RF OVR7 ADR70

ADR7RF : ADR7RF
bits : 0 - 0 (1 bit)
access : read-only

OVR7 : OVR7
bits : 1 - 1 (1 bit)
access : read-only

ADR70 : ADR70
bits : 4 - 15 (12 bit)
access : read-only


MOD0

AD Mode Setting Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD0 MOD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSS DACON

ADSS : ADSS
bits : 0 - 0 (1 bit)
access : write-only

DACON : DACON
bits : 1 - 1 (1 bit)
access : read-write


REG8

AD Conversion Result Register 8
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG8 REG8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR8RF OVR8 ADR80

ADR8RF : ADR8RF
bits : 0 - 0 (1 bit)
access : read-only

OVR8 : OVR8
bits : 1 - 1 (1 bit)
access : read-only

ADR80 : ADR80
bits : 4 - 15 (12 bit)
access : read-only


REG9

AD Conversion Result Register 9
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG9 REG9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR9RF OVR9 ADR90

ADR9RF : ADR9RF
bits : 0 - 0 (1 bit)
access : read-only

OVR9 : OVR9
bits : 1 - 1 (1 bit)
access : read-only

ADR90 : ADR90
bits : 4 - 15 (12 bit)
access : read-only


REG10

AD Conversion Result Register 10
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG10 REG10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR10RF OVR10 ADR100

ADR10RF : ADR10RF
bits : 0 - 0 (1 bit)
access : read-only

OVR10 : OVR10
bits : 1 - 1 (1 bit)
access : read-only

ADR100 : ADR100
bits : 4 - 15 (12 bit)
access : read-only


REG11

AD Conversion Result Register 11
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG11 REG11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR11RF OVR11 ADR110

ADR11RF : ADR11RF
bits : 0 - 0 (1 bit)
access : read-only

OVR11 : OVR11
bits : 1 - 1 (1 bit)
access : read-only

ADR110 : ADR110
bits : 4 - 15 (12 bit)
access : read-only


PSEL6

PMD Trigger Program Number Select Register 6
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL6 PSEL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMDS6 PENS6

PMDS6 : PMDS6
bits : 0 - 2 (3 bit)
access : read-write

PENS6 : PENS6
bits : 7 - 7 (1 bit)
access : read-write


PSEL7

PMD Trigger Program Number Select Register 7
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL7 PSEL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMDS7 PENS7

PMDS7 : PMDS7
bits : 0 - 2 (3 bit)
access : read-write

PENS7 : PENS7
bits : 7 - 7 (1 bit)
access : read-write


PSEL8

PMD Trigger Program Number Select Register 8
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL8 PSEL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMDS8 PENS8

PMDS8 : PMDS8
bits : 0 - 2 (3 bit)
access : read-write

PENS8 : PENS8
bits : 7 - 7 (1 bit)
access : read-write


PSEL9

PMD Trigger Program Number Select Register 9
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL9 PSEL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMDS9 PENS9

PMDS9 : PMDS9
bits : 0 - 2 (3 bit)
access : read-write

PENS9 : PENS9
bits : 7 - 7 (1 bit)
access : read-write


PSEL10

PMD Trigger Program Number Select Register 10
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL10 PSEL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMDS10 PENS10

PMDS10 : PMDS10
bits : 0 - 2 (3 bit)
access : read-write

PENS10 : PENS10
bits : 7 - 7 (1 bit)
access : read-write


PSEL11

PMD Trigger Program Number Select Register 11
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL11 PSEL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMDS11 PENS11

PMDS11 : PMDS11
bits : 0 - 2 (3 bit)
access : read-write

PENS11 : PENS11
bits : 7 - 7 (1 bit)
access : read-write


MOD1

AD Mode Setting Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD1 MOD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADAS ADEN

ADAS : ADAS
bits : 0 - 0 (1 bit)
access : read-write

ADEN : ADEN
bits : 7 - 7 (1 bit)
access : read-write


PINTS0

PMD Trigger Interrupt Select Register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTS0 PINTS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL0

INTSEL0 : INTSEL0
bits : 0 - 1 (2 bit)
access : read-write


PINTS1

PMD Trigger Interrupt Select Register 1
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTS1 PINTS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL1

INTSEL1 : INTSEL1
bits : 0 - 1 (2 bit)
access : read-write


PINTS2

PMD Trigger Interrupt Select Register 2
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTS2 PINTS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL2

INTSEL2 : INTSEL2
bits : 0 - 1 (2 bit)
access : read-write


PINTS3

PMD Trigger Interrupt Select Register 3
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTS3 PINTS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL3

INTSEL3 : INTSEL3
bits : 0 - 1 (2 bit)
access : read-write


PINTS4

PMD Trigger Interrupt Select Register 4
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTS4 PINTS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL4

INTSEL4 : INTSEL4
bits : 0 - 1 (2 bit)
access : read-write


PINTS5

PMD Trigger Interrupt Select Register 5
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTS5 PINTS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL5

INTSEL5 : INTSEL5
bits : 0 - 1 (2 bit)
access : read-write


PSET0

PMD Trigger Program Register 0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET0 PSET0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSP00 UVWIS00 ENSP00 AINSP01 UVWIS01 ENSP01 AINSP02 UVWIS02 ENSP02 AINSP03 UVWIS03 ENSP03

AINSP00 : AINSP00
bits : 0 - 4 (5 bit)
access : read-write

UVWIS00 : UVWIS00
bits : 5 - 6 (2 bit)
access : read-write

ENSP00 : ENSP00
bits : 7 - 7 (1 bit)
access : read-write

AINSP01 : AINSP01
bits : 8 - 12 (5 bit)
access : read-write

UVWIS01 : UVWIS01
bits : 13 - 14 (2 bit)
access : read-write

ENSP01 : ENSP01
bits : 15 - 15 (1 bit)
access : read-write

AINSP02 : AINSP02
bits : 16 - 20 (5 bit)
access : read-write

UVWIS02 : UVWIS02
bits : 21 - 22 (2 bit)
access : read-write

ENSP02 : ENSP02
bits : 23 - 23 (1 bit)
access : read-write

AINSP03 : AINSP03
bits : 24 - 28 (5 bit)
access : read-write

UVWIS03 : UVWIS03
bits : 29 - 30 (2 bit)
access : read-write

ENSP03 : ENSP03
bits : 31 - 31 (1 bit)
access : read-write


PSET1

PMD Trigger Program Register 1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET1 PSET1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSP10 UVWIS10 ENSP10 AINSP11 UVWIS11 ENSP11 AINSP12 UVWIS12 ENSP12 AINSP13 UVWIS13 ENSP13

AINSP10 : AINSP10
bits : 0 - 4 (5 bit)
access : read-write

UVWIS10 : UVWIS10
bits : 5 - 6 (2 bit)
access : read-write

ENSP10 : ENSP10
bits : 7 - 7 (1 bit)
access : read-write

AINSP11 : AINSP11
bits : 8 - 12 (5 bit)
access : read-write

UVWIS11 : UVWIS11
bits : 13 - 14 (2 bit)
access : read-write

ENSP11 : ENSP11
bits : 15 - 15 (1 bit)
access : read-write

AINSP12 : AINSP12
bits : 16 - 20 (5 bit)
access : read-write

UVWIS12 : UVWIS12
bits : 21 - 22 (2 bit)
access : read-write

ENSP12 : ENSP12
bits : 23 - 23 (1 bit)
access : read-write

AINSP13 : AINSP13
bits : 24 - 28 (5 bit)
access : read-write

UVWIS13 : UVWIS13
bits : 29 - 30 (2 bit)
access : read-write

ENSP13 : ENSP13
bits : 31 - 31 (1 bit)
access : read-write


PSET2

PMD Trigger Program Register 2
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET2 PSET2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSP20 UVWIS20 ENSP20 AINSP21 UVWIS21 ENSP21 AINSP22 UVWIS22 ENSP22 AINSP23 UVWIS23 ENSP23

AINSP20 : AINSP20
bits : 0 - 4 (5 bit)
access : read-write

UVWIS20 : UVWIS20
bits : 5 - 6 (2 bit)
access : read-write

ENSP20 : ENSP20
bits : 7 - 7 (1 bit)
access : read-write

AINSP21 : AINSP21
bits : 8 - 12 (5 bit)
access : read-write

UVWIS21 : UVWIS21
bits : 13 - 14 (2 bit)
access : read-write

ENSP21 : ENSP21
bits : 15 - 15 (1 bit)
access : read-write

AINSP22 : AINSP22
bits : 16 - 20 (5 bit)
access : read-write

UVWIS22 : UVWIS22
bits : 21 - 22 (2 bit)
access : read-write

ENSP22 : ENSP22
bits : 23 - 23 (1 bit)
access : read-write

AINSP23 : AINSP23
bits : 24 - 28 (5 bit)
access : read-write

UVWIS23 : UVWIS23
bits : 29 - 30 (2 bit)
access : read-write

ENSP23 : ENSP23
bits : 31 - 31 (1 bit)
access : read-write


PSET3

PMD Trigger Program Register 3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET3 PSET3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSP30 UVWIS30 ENSP30 AINSP31 UVWIS31 ENSP31 AINSP32 UVWIS32 ENSP32 AINSP33 UVWIS33 ENSP33

AINSP30 : AINSP30
bits : 0 - 4 (5 bit)
access : read-write

UVWIS30 : UVWIS30
bits : 5 - 6 (2 bit)
access : read-write

ENSP30 : ENSP30
bits : 7 - 7 (1 bit)
access : read-write

AINSP31 : AINSP31
bits : 8 - 12 (5 bit)
access : read-write

UVWIS31 : UVWIS31
bits : 13 - 14 (2 bit)
access : read-write

ENSP31 : ENSP31
bits : 15 - 15 (1 bit)
access : read-write

AINSP32 : AINSP32
bits : 16 - 20 (5 bit)
access : read-write

UVWIS32 : UVWIS32
bits : 21 - 22 (2 bit)
access : read-write

ENSP32 : ENSP32
bits : 23 - 23 (1 bit)
access : read-write

AINSP33 : AINSP33
bits : 24 - 28 (5 bit)
access : read-write

UVWIS33 : UVWIS33
bits : 29 - 30 (2 bit)
access : read-write

ENSP33 : ENSP33
bits : 31 - 31 (1 bit)
access : read-write


PSET4

PMD Trigger Program Register 4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET4 PSET4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSP40 UVWIS40 ENSP40 AINSP41 UVWIS41 ENSP41 AINSP42 UVWIS42 ENSP42 AINSP43 UVWIS43 ENSP43

AINSP40 : AINSP40
bits : 0 - 4 (5 bit)
access : read-write

UVWIS40 : UVWIS40
bits : 5 - 6 (2 bit)
access : read-write

ENSP40 : ENSP40
bits : 7 - 7 (1 bit)
access : read-write

AINSP41 : AINSP41
bits : 8 - 12 (5 bit)
access : read-write

UVWIS41 : UVWIS41
bits : 13 - 14 (2 bit)
access : read-write

ENSP41 : ENSP41
bits : 15 - 15 (1 bit)
access : read-write

AINSP42 : AINSP42
bits : 16 - 20 (5 bit)
access : read-write

UVWIS42 : UVWIS42
bits : 21 - 22 (2 bit)
access : read-write

ENSP42 : ENSP42
bits : 23 - 23 (1 bit)
access : read-write

AINSP43 : AINSP43
bits : 24 - 28 (5 bit)
access : read-write

UVWIS43 : UVWIS43
bits : 29 - 30 (2 bit)
access : read-write

ENSP43 : ENSP43
bits : 31 - 31 (1 bit)
access : read-write


PSET5

PMD Trigger Program Register 5
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET5 PSET5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSP50 UVWIS50 ENSP50 AINSP51 UVWIS51 ENSP51 AINSP52 UVWIS52 ENSP52 AINSP53 UVWIS53 ENSP53

AINSP50 : AINSP50
bits : 0 - 4 (5 bit)
access : read-write

UVWIS50 : UVWIS50
bits : 5 - 6 (2 bit)
access : read-write

ENSP50 : ENSP50
bits : 7 - 7 (1 bit)
access : read-write

AINSP51 : AINSP51
bits : 8 - 12 (5 bit)
access : read-write

UVWIS51 : UVWIS51
bits : 13 - 14 (2 bit)
access : read-write

ENSP51 : ENSP51
bits : 15 - 15 (1 bit)
access : read-write

AINSP52 : AINSP52
bits : 16 - 20 (5 bit)
access : read-write

UVWIS52 : UVWIS52
bits : 21 - 22 (2 bit)
access : read-write

ENSP52 : ENSP52
bits : 23 - 23 (1 bit)
access : read-write

AINSP53 : AINSP53
bits : 24 - 28 (5 bit)
access : read-write

UVWIS53 : UVWIS53
bits : 29 - 30 (2 bit)
access : read-write

ENSP53 : ENSP53
bits : 31 - 31 (1 bit)
access : read-write


TSET03

Timer Trigger Program Register 03
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSET03 TSET03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINST0 ENST0 AINST1 ENST1 AINST2 ENST2 AINST3 ENST3

AINST0 : AINST0
bits : 0 - 4 (5 bit)
access : read-write

ENST0 : ENST0
bits : 7 - 7 (1 bit)
access : read-write

AINST1 : AINST1
bits : 8 - 12 (5 bit)
access : read-write

ENST1 : ENST1
bits : 15 - 15 (1 bit)
access : read-write

AINST2 : AINST2
bits : 16 - 20 (5 bit)
access : read-write

ENST2 : ENST2
bits : 23 - 23 (1 bit)
access : read-write

AINST3 : AINST3
bits : 24 - 28 (5 bit)
access : read-write

ENST3 : ENST3
bits : 31 - 31 (1 bit)
access : read-write


TSET47

Timer Trigger Program Register 47
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSET47 TSET47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINST4 ENST4 AINST5 ENST5 AINST6 ENST6 AINST7 ENST7

AINST4 : AINST4
bits : 0 - 4 (5 bit)
access : read-write

ENST4 : ENST4
bits : 7 - 7 (1 bit)
access : read-write

AINST5 : AINST5
bits : 8 - 12 (5 bit)
access : read-write

ENST5 : ENST5
bits : 15 - 15 (1 bit)
access : read-write

AINST6 : AINST6
bits : 16 - 20 (5 bit)
access : read-write

ENST6 : ENST6
bits : 23 - 23 (1 bit)
access : read-write

AINST7 : AINST7
bits : 24 - 28 (5 bit)
access : read-write

ENST7 : ENST7
bits : 31 - 31 (1 bit)
access : read-write


TSET811

Timer Trigger Program Register 811
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSET811 TSET811 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINST8 ENST8 AINST9 ENST9 AINST10 ENST10 AINST11 ENST11

AINST8 : AINST8
bits : 0 - 4 (5 bit)
access : read-write

ENST8 : ENST8
bits : 7 - 7 (1 bit)
access : read-write

AINST9 : AINST9
bits : 8 - 12 (5 bit)
access : read-write

ENST9 : ENST9
bits : 15 - 15 (1 bit)
access : read-write

AINST10 : AINST10
bits : 16 - 20 (5 bit)
access : read-write

ENST10 : ENST10
bits : 23 - 23 (1 bit)
access : read-write

AINST11 : AINST11
bits : 24 - 28 (5 bit)
access : read-write

ENST11 : ENST11
bits : 31 - 31 (1 bit)
access : read-write


SSET03

Software Trigger Program Register 03
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSET03 SSET03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSS0 ENSS0 AINSS1 ENSS1 AINSS2 ENSS2 AINSS3 ENSS3

AINSS0 : AINSS0
bits : 0 - 4 (5 bit)
access : read-write

ENSS0 : ENSS0
bits : 7 - 7 (1 bit)
access : read-write

AINSS1 : AINSS1
bits : 8 - 12 (5 bit)
access : read-write

ENSS1 : ENSS1
bits : 15 - 15 (1 bit)
access : read-write

AINSS2 : AINSS2
bits : 16 - 20 (5 bit)
access : read-write

ENSS2 : ENSS2
bits : 23 - 23 (1 bit)
access : read-write

AINSS3 : AINSS3
bits : 24 - 28 (5 bit)
access : read-write

ENSS3 : ENSS3
bits : 31 - 31 (1 bit)
access : read-write


MOD2

AD Mode Setting Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MOD2 MOD2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBFN ADSFN

ADBFN : ADBFN
bits : 0 - 0 (1 bit)
access : read-only

ADSFN : ADSFN
bits : 1 - 1 (1 bit)
access : read-only


SSET47

Software Trigger Program Register 47
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSET47 SSET47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSS4 ENSS4 AINSS5 ENSS5 AINSS6 ENSS6 AINSS7 ENSS7

AINSS4 : AINSS4
bits : 0 - 4 (5 bit)
access : read-write

ENSS4 : ENSS4
bits : 7 - 7 (1 bit)
access : read-write

AINSS5 : AINSS5
bits : 8 - 12 (5 bit)
access : read-write

ENSS5 : ENSS5
bits : 15 - 15 (1 bit)
access : read-write

AINSS6 : AINSS6
bits : 16 - 20 (5 bit)
access : read-write

ENSS6 : ENSS6
bits : 23 - 23 (1 bit)
access : read-write

AINSS7 : AINSS7
bits : 24 - 28 (5 bit)
access : read-write

ENSS7 : ENSS7
bits : 31 - 31 (1 bit)
access : read-write


SSET811

Software Trigger Program Register 811
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSET811 SSET811 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSS8 ENSS8 AINSS9 ENSS9 AINSS10 ENSS10 AINSS11 ENSS11

AINSS8 : AINSS8
bits : 0 - 4 (5 bit)
access : read-write

ENSS8 : ENSS8
bits : 7 - 7 (1 bit)
access : read-write

AINSS9 : AINSS9
bits : 8 - 12 (5 bit)
access : read-write

ENSS9 : ENSS9
bits : 15 - 15 (1 bit)
access : read-write

AINSS10 : AINSS10
bits : 16 - 20 (5 bit)
access : read-write

ENSS10 : ENSS10
bits : 23 - 23 (1 bit)
access : read-write

AINSS11 : AINSS11
bits : 24 - 28 (5 bit)
access : read-write

ENSS11 : ENSS11
bits : 31 - 31 (1 bit)
access : read-write


ASET03

Constant Conversion Program Register 03
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASET03 ASET03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSA0 ENSA0 AINSA1 ENSA1 AINSA2 ENSA2 AINSA3 ENSA3

AINSA0 : AINSA0
bits : 0 - 4 (5 bit)
access : read-write

ENSA0 : ENSA0
bits : 7 - 7 (1 bit)
access : read-write

AINSA1 : AINSA1
bits : 8 - 12 (5 bit)
access : read-write

ENSA1 : ENSA1
bits : 15 - 15 (1 bit)
access : read-write

AINSA2 : AINSA2
bits : 16 - 20 (5 bit)
access : read-write

ENSA2 : ENSA2
bits : 23 - 23 (1 bit)
access : read-write

AINSA3 : AINSA3
bits : 24 - 28 (5 bit)
access : read-write

ENSA3 : ENSA3
bits : 31 - 31 (1 bit)
access : read-write


ASET47

Constant Conversion Program Register 47
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASET47 ASET47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSA4 ENSA4 AINSA5 ENSA5 AINSA6 ENSA6 AINSA7 ENSA7

AINSA4 : AINSA4
bits : 0 - 4 (5 bit)
access : read-write

ENSA4 : ENSA4
bits : 7 - 7 (1 bit)
access : read-write

AINSA5 : AINSA5
bits : 8 - 12 (5 bit)
access : read-write

ENSA5 : ENSA5
bits : 15 - 15 (1 bit)
access : read-write

AINSA6 : AINSA6
bits : 16 - 20 (5 bit)
access : read-write

ENSA6 : ENSA6
bits : 23 - 23 (1 bit)
access : read-write

AINSA7 : AINSA7
bits : 24 - 28 (5 bit)
access : read-write

ENSA7 : ENSA7
bits : 31 - 31 (1 bit)
access : read-write


ASET811

Constant Conversion Program Register 811
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASET811 ASET811 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINSA8 ENSA8 AINSA9 ENSA9 AINSA10 ENSA10 AINSA11 ENSA11

AINSA8 : AINSA8
bits : 0 - 4 (5 bit)
access : read-write

ENSA8 : ENSA8
bits : 7 - 7 (1 bit)
access : read-write

AINSA9 : AINSA9
bits : 8 - 12 (5 bit)
access : read-write

ENSA9 : ENSA9
bits : 15 - 15 (1 bit)
access : read-write

AINSA10 : AINSA10
bits : 16 - 20 (5 bit)
access : read-write

ENSA10 : ENSA10
bits : 23 - 23 (1 bit)
access : read-write

AINSA11 : AINSA11
bits : 24 - 28 (5 bit)
access : read-write

ENSA11 : ENSA11
bits : 31 - 31 (1 bit)
access : read-write


MOD3

Mode setting Register3
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD3 MOD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMODE RCUT

PMODE : PMODE
bits : 3 - 5 (3 bit)
access : read-write

RCUT : RCUT
bits : 8 - 8 (1 bit)
access : read-write



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