\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected
EPHC Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
SWRST : SWRST
bits : 6 - 7 (2 bit)
access : write-only
EPHC 16-bit Counter Run Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUN : RUN
bits : 0 - 0 (1 bit)
access : read-write
CLR : CLR
bits : 1 - 1 (1 bit)
access : read-write
EPHC Pulse Counter Compare 0 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP0 : CMP0
bits : 0 - 15 (16 bit)
access : read-write
EPHC Pulse Counter Compare 1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP1 : CMP1
bits : 0 - 15 (16 bit)
access : read-write
EPHC 16-bit Counter Read Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : DAT
bits : 0 - 15 (16 bit)
access : read-write
PMF : PMF
bits : 30 - 30 (1 bit)
access : read-only
PHCDIRF : PHCDIRF
bits : 31 - 31 (1 bit)
access : read-only
EPHC 24-bit Counter Run Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T24RUN : T24RUN
bits : 0 - 0 (1 bit)
access : read-write
EPHC DMAE Request Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMADT0 : DMADT0
bits : 0 - 0 (1 bit)
access : read-write
DMADT1 : DMADT1
bits : 1 - 1 (1 bit)
access : read-write
EPHC 24-bit Counter Read Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
T24UCR : T24UCR
bits : 0 - 23 (24 bit)
access : read-only
EPHC Capture 00 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP00 : CAP00
bits : 0 - 23 (24 bit)
access : read-only
OVF00 : OVF00
bits : 24 - 24 (1 bit)
access : read-only
EPHC Capture 10 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP10 : CAP10
bits : 0 - 23 (24 bit)
access : read-only
OVF10 : OVF10
bits : 24 - 24 (1 bit)
access : read-only
EPHC Capture 20 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP20 : CAP20
bits : 0 - 23 (24 bit)
access : read-only
OVF20 : OVF20
bits : 24 - 24 (1 bit)
access : read-only
EPHC Capture 30 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP30 : CAP30
bits : 0 - 23 (24 bit)
access : read-only
OVF30 : OVF30
bits : 24 - 24 (1 bit)
access : read-only
EPHC Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA1DN : MA1DN
bits : 0 - 2 (3 bit)
access : read-write
MA1UP : MA1UP
bits : 4 - 6 (3 bit)
access : read-write
BRCK : BRCK
bits : 8 - 9 (2 bit)
access : read-write
PBMOD : PBMOD
bits : 10 - 10 (1 bit)
access : read-write
PBDIR : PBDIR
bits : 11 - 11 (1 bit)
access : read-write
MA12 : MA12
bits : 12 - 12 (1 bit)
access : read-write
MA2DIR : MA2DIR
bits : 13 - 13 (1 bit)
access : read-write
NF : NF
bits : 14 - 15 (2 bit)
access : read-write
DATSEL : DATSEL
bits : 16 - 17 (2 bit)
access : read-write
LWLMEN : LWLMEN
bits : 18 - 18 (1 bit)
access : read-write
UPLMEN : UPLMEN
bits : 19 - 19 (1 bit)
access : read-write
LOADLMT : LOADLMT
bits : 20 - 20 (1 bit)
access : write-only
EPHC Cycle 0 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B0DAT : B0DAT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Cycle 1 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B1DAT : B1DAT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Cycle 2 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B2DAT : B2DAT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Cycle 3 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B3DAT : B3DAT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Cycle Common Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BCDAT : BCDAT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Phase DifferEPHCe 0 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B0PDT : B0PDT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Phase DifferEPHCe 1 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B1PDT : B1PDT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Phase DifferEPHCe 2 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B2PDT : B2PDT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Phase DifferEPHCe 3 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B3PDT : B3PDT
bits : 0 - 23 (24 bit)
access : read-only
EPHC Upper Cycle Limit Value Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLMT : UPLMT
bits : 0 - 23 (24 bit)
access : read-write
EPHC Lower Cycle Limit Value Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LWLMT : LWLMT
bits : 0 - 23 (24 bit)
access : read-write
EPHC Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPCCP0 : INTPCCP0
bits : 0 - 0 (1 bit)
access : read-write
INTPCCP1 : INTPCCP1
bits : 1 - 1 (1 bit)
access : read-write
INTPCOVF : INTPCOVF
bits : 2 - 2 (1 bit)
access : read-write
INTPCUDF : INTPCUDF
bits : 3 - 3 (1 bit)
access : read-write
INTPCDT0 : INTPCDT0
bits : 4 - 4 (1 bit)
access : read-write
INTPCDT1 : INTPCDT1
bits : 5 - 5 (1 bit)
access : read-write
INTPCDT2 : INTPCDT2
bits : 6 - 6 (1 bit)
access : read-write
INTPCDT3 : INTPCDT3
bits : 7 - 7 (1 bit)
access : read-write
INTPCDIR : INTPCDIR
bits : 8 - 8 (1 bit)
access : read-write
INTPCUOVF : INTPCUOVF
bits : 9 - 9 (1 bit)
access : read-write
INTLWLMT : INTLWLMT
bits : 10 - 10 (1 bit)
access : read-write
INTUPLMT : INTUPLMT
bits : 11 - 11 (1 bit)
access : read-write
EPHC Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP0F : CMP0F
bits : 0 - 0 (1 bit)
access : read-write
CMP1F : CMP1F
bits : 1 - 1 (1 bit)
access : read-write
OVFF : OVFF
bits : 2 - 2 (1 bit)
access : read-write
UDFF : UDFF
bits : 3 - 3 (1 bit)
access : read-write
SB0F : SB0F
bits : 4 - 4 (1 bit)
access : read-write
SB1F : SB1F
bits : 5 - 5 (1 bit)
access : read-write
SB2F : SB2F
bits : 6 - 6 (1 bit)
access : read-write
SB3F : SB3F
bits : 7 - 7 (1 bit)
access : read-write
DIRF : DIRF
bits : 8 - 8 (1 bit)
access : read-write
LWLMT : LWLMT
bits : 9 - 9 (1 bit)
access : read-write
UPLMT : UPLMT
bits : 10 - 10 (1 bit)
access : read-write
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