\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : reserved
protection : not protected
Port G Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG0 : PG0
bits : 0 - 0 (1 bit)
access : read-write
PG1 : PG1
bits : 1 - 1 (1 bit)
access : read-write
PG2 : PG2
bits : 2 - 2 (1 bit)
access : read-write
PG3 : PG3
bits : 3 - 3 (1 bit)
access : read-write
PG4 : PG4
bits : 4 - 4 (1 bit)
access : read-write
PG5 : PG5
bits : 5 - 5 (1 bit)
access : read-write
Port G Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG0UP : PG0UP
bits : 0 - 0 (1 bit)
access : read-write
PG1UP : PG1UP
bits : 1 - 1 (1 bit)
access : read-write
PG2UP : PG2UP
bits : 2 - 2 (1 bit)
access : read-write
PG3UP : PG3UP
bits : 3 - 3 (1 bit)
access : read-write
PG4UP : PG4UP
bits : 4 - 4 (1 bit)
access : read-write
PG5UP : PG5UP
bits : 5 - 5 (1 bit)
access : read-write
Port G Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG0IE : PG0IE
bits : 0 - 0 (1 bit)
access : read-write
PG1IE : PG1IE
bits : 1 - 1 (1 bit)
access : read-write
PG2IE : PG2IE
bits : 2 - 2 (1 bit)
access : read-write
PG3IE : PG3IE
bits : 3 - 3 (1 bit)
access : read-write
PG4IE : PG4IE
bits : 4 - 4 (1 bit)
access : read-write
PG5IE : PG5IE
bits : 5 - 5 (1 bit)
access : read-write
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