\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0xE4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x104 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : reserved
protection : not protected
TSPI Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSPIE : TSPIE
bits : 0 - 0 (1 bit)
access : read-write
SWRST : SWRST
bits : 6 - 7 (2 bit)
access : write-only
TSPI Baud Rate Generator Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRS : BRS
bits : 0 - 3 (4 bit)
access : read-write
BRCK : BRCK
bits : 4 - 7 (4 bit)
access : read-write
TSPI Data Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSPIDR : TSPIDR
bits : 0 - 31 (32 bit)
access : read-write
TSPI Format Control Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCKCSDL : SCKCSDL
bits : 0 - 3 (4 bit)
access : read-write
CSSCKDL : CSSCKDL
bits : 4 - 7 (4 bit)
access : read-write
CSINT : CSINT
bits : 10 - 13 (4 bit)
access : read-write
CKPOL : CKPOL
bits : 14 - 14 (1 bit)
access : read-write
CKPHA : CKPHA
bits : 15 - 15 (1 bit)
access : read-write
CS0POL : CS0POL
bits : 16 - 16 (1 bit)
access : read-write
CS1POL : CS1POL
bits : 17 - 17 (1 bit)
access : read-write
CS2POL : CS2POL
bits : 18 - 18 (1 bit)
access : read-write
CS3POL : CS3POL
bits : 19 - 19 (1 bit)
access : read-write
FINT : FINT
bits : 20 - 23 (4 bit)
access : read-write
FL : FL
bits : 24 - 29 (6 bit)
access : read-write
DIR : DIR
bits : 31 - 31 (1 bit)
access : read-write
TSPI Format Control Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VPM : VPM
bits : 0 - 0 (1 bit)
access : read-write
VPE : VPE
bits : 1 - 1 (1 bit)
access : read-write
EHOLD : EHOLD
bits : 4 - 6 (3 bit)
access : read-write
TSPI Status Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RLVL : RLVL
bits : 0 - 3 (4 bit)
access : read-only
RFFLL : RFFLL
bits : 4 - 4 (1 bit)
access : read-only
INTRXFF : INTRXFF
bits : 5 - 5 (1 bit)
access : read-write
RXEND : RXEND
bits : 6 - 6 (1 bit)
access : read-write
RXRUN : RXRUN
bits : 7 - 7 (1 bit)
access : read-only
TLVL : TLVL
bits : 16 - 19 (4 bit)
access : read-only
TFEMP : TFEMP
bits : 20 - 20 (1 bit)
access : read-only
INTTXWF : INTTXWF
bits : 21 - 21 (1 bit)
access : read-write
TXEND : TXEND
bits : 22 - 22 (1 bit)
access : read-write
TXRUN : TXRUN
bits : 23 - 23 (1 bit)
access : read-only
TSPISUE : TSPISUE
bits : 31 - 31 (1 bit)
access : read-only
TSPI Parity Error Flag Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERR : PERR
bits : 0 - 0 (1 bit)
access : read-write
OVRERR : OVRERR
bits : 1 - 1 (1 bit)
access : read-write
UDRERR : UDRERR
bits : 2 - 2 (1 bit)
access : read-write
TRGERR : TRGERR
bits : 3 - 3 (1 bit)
access : read-write
TSPI Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC : FC
bits : 0 - 7 (8 bit)
access : read-write
CSSEL : CSSEL
bits : 8 - 9 (2 bit)
access : read-write
TMMD : TMMD
bits : 10 - 11 (2 bit)
access : read-write
MSTR : MSTR
bits : 12 - 12 (1 bit)
access : read-write
TSPIMS : TSPIMS
bits : 13 - 13 (1 bit)
access : read-write
TRXE : TRXE
bits : 14 - 14 (1 bit)
access : read-write
TRGEN : TRGEN
bits : 15 - 15 (1 bit)
access : read-write
TSPI Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMARE : DMARE
bits : 0 - 0 (1 bit)
access : read-write
DMATE : DMATE
bits : 1 - 1 (1 bit)
access : read-write
INTERR : INTERR
bits : 2 - 2 (1 bit)
access : read-write
INTRXWE : INTRXWE
bits : 4 - 4 (1 bit)
access : read-write
INTRXFE : INTRXFE
bits : 5 - 5 (1 bit)
access : read-write
INTTXWE : INTTXWE
bits : 6 - 6 (1 bit)
access : read-write
INTTXFE : INTTXFE
bits : 7 - 7 (1 bit)
access : read-write
RIL : RIL
bits : 8 - 11 (4 bit)
access : read-write
TIL : TIL
bits : 12 - 15 (4 bit)
access : read-write
RXDLY : RXDLY
bits : 16 - 16 (1 bit)
access : read-write
TXDEMP : TXDEMP
bits : 21 - 21 (1 bit)
access : read-write
TIDLE : TIDLE
bits : 22 - 23 (2 bit)
access : read-write
TSPI Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFFLLCLR : RFFLLCLR
bits : 0 - 0 (1 bit)
access : write-only
TFEMPCLR : TFEMPCLR
bits : 1 - 1 (1 bit)
access : write-only
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