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TSEL0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR0

CR4

CR5

CR6

CR7

CR8

CR9

CR10

CR11

CR12

CR13

CR14

CR15

CR1

CR2

CR3


CR0

TRGSEL Control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 OUTSEL0 UPDN0 INSEL0 EN1 OUTSEL1 UPDN1 INSEL1 EN2 OUTSEL2 UPDN2 INSEL2 EN3 OUTSEL3 UPDN3 INSEL3

EN0 : EN0
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL0 : OUTSEL0
bits : 1 - 1 (1 bit)
access : read-write

UPDN0 : UPDN0
bits : 2 - 2 (1 bit)
access : read-write

INSEL0 : INSEL0
bits : 4 - 6 (3 bit)
access : read-write

EN1 : EN1
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL1 : OUTSEL1
bits : 9 - 9 (1 bit)
access : read-write

UPDN1 : UPDN1
bits : 10 - 10 (1 bit)
access : read-write

INSEL1 : INSEL1
bits : 12 - 14 (3 bit)
access : read-write

EN2 : EN2
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL2 : OUTSEL2
bits : 17 - 17 (1 bit)
access : read-write

UPDN2 : UPDN2
bits : 18 - 18 (1 bit)
access : read-write

INSEL2 : INSEL2
bits : 20 - 22 (3 bit)
access : read-write

EN3 : EN3
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL3 : OUTSEL3
bits : 25 - 25 (1 bit)
access : read-write

UPDN3 : UPDN3
bits : 26 - 26 (1 bit)
access : read-write

INSEL3 : INSEL3
bits : 28 - 30 (3 bit)
access : read-write


CR4

TRGSEL Control register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR4 CR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN16 OUTSEL16 UPDN16 INSEL16 EN17 OUTSEL17 UPDN17 INSEL17 EN18 OUTSEL18 UPDN18 INSEL18 EN19 OUTSEL19 UPDN19 INSEL19

EN16 : EN16
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL16 : OUTSEL16
bits : 1 - 1 (1 bit)
access : read-write

UPDN16 : UPDN16
bits : 2 - 2 (1 bit)
access : read-write

INSEL16 : INSEL16
bits : 4 - 6 (3 bit)
access : read-write

EN17 : EN17
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL17 : OUTSEL17
bits : 9 - 9 (1 bit)
access : read-write

UPDN17 : UPDN17
bits : 10 - 10 (1 bit)
access : read-write

INSEL17 : INSEL17
bits : 12 - 14 (3 bit)
access : read-write

EN18 : EN18
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL18 : OUTSEL18
bits : 17 - 17 (1 bit)
access : read-write

UPDN18 : UPDN18
bits : 18 - 18 (1 bit)
access : read-write

INSEL18 : INSEL18
bits : 20 - 22 (3 bit)
access : read-write

EN19 : EN19
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL19 : OUTSEL19
bits : 25 - 25 (1 bit)
access : read-write

UPDN19 : UPDN19
bits : 26 - 26 (1 bit)
access : read-write

INSEL19 : INSEL19
bits : 28 - 30 (3 bit)
access : read-write


CR5

TRGSEL Control register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR5 CR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN20 OUTSEL20 UPDN20 INSEL20 EN21 OUTSEL21 UPDN21 INSEL21 EN22 OUTSEL22 UPDN22 INSEL22 EN23 OUTSEL23 UPDN23 INSEL23

EN20 : EN20
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL20 : OUTSEL20
bits : 1 - 1 (1 bit)
access : read-write

UPDN20 : UPDN20
bits : 2 - 2 (1 bit)
access : read-write

INSEL20 : INSEL20
bits : 4 - 6 (3 bit)
access : read-write

EN21 : EN21
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL21 : OUTSEL21
bits : 9 - 9 (1 bit)
access : read-write

UPDN21 : UPDN21
bits : 10 - 10 (1 bit)
access : read-write

INSEL21 : INSEL21
bits : 12 - 14 (3 bit)
access : read-write

EN22 : EN22
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL22 : OUTSEL22
bits : 17 - 17 (1 bit)
access : read-write

UPDN22 : UPDN22
bits : 18 - 18 (1 bit)
access : read-write

INSEL22 : INSEL22
bits : 20 - 22 (3 bit)
access : read-write

EN23 : EN23
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL23 : OUTSEL23
bits : 25 - 25 (1 bit)
access : read-write

UPDN23 : UPDN23
bits : 26 - 26 (1 bit)
access : read-write

INSEL23 : INSEL23
bits : 28 - 30 (3 bit)
access : read-write


CR6

TRGSEL Control register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR6 CR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN24 OUTSEL24 UPDN24 INSEL24 EN25 OUTSEL25 UPDN25 INSEL25 EN26 OUTSEL26 UPDN26 INSEL26 EN27 OUTSEL27 UPDN27 INSEL27

EN24 : EN24
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL24 : OUTSEL24
bits : 1 - 1 (1 bit)
access : read-write

UPDN24 : UPDN24
bits : 2 - 2 (1 bit)
access : read-write

INSEL24 : INSEL24
bits : 4 - 6 (3 bit)
access : read-write

EN25 : EN25
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL25 : OUTSEL25
bits : 9 - 9 (1 bit)
access : read-write

UPDN25 : UPDN25
bits : 10 - 10 (1 bit)
access : read-write

INSEL25 : INSEL25
bits : 12 - 14 (3 bit)
access : read-write

EN26 : EN26
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL26 : OUTSEL26
bits : 17 - 17 (1 bit)
access : read-write

UPDN26 : UPDN26
bits : 18 - 18 (1 bit)
access : read-write

INSEL26 : INSEL26
bits : 20 - 22 (3 bit)
access : read-write

EN27 : EN27
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL27 : OUTSEL27
bits : 25 - 25 (1 bit)
access : read-write

UPDN27 : UPDN27
bits : 26 - 26 (1 bit)
access : read-write

INSEL27 : INSEL27
bits : 28 - 30 (3 bit)
access : read-write


CR7

TRGSEL Control register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR7 CR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN28 OUTSEL28 UPDN28 INSEL28 EN29 OUTSEL29 UPDN29 INSEL29 EN30 OUTSEL30 UPDN30 INSEL30 EN31 OUTSEL31 UPDN31 INSEL31

EN28 : EN28
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL28 : OUTSEL28
bits : 1 - 1 (1 bit)
access : read-write

UPDN28 : UPDN28
bits : 2 - 2 (1 bit)
access : read-write

INSEL28 : INSEL28
bits : 4 - 6 (3 bit)
access : read-write

EN29 : EN29
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL29 : OUTSEL29
bits : 9 - 9 (1 bit)
access : read-write

UPDN29 : UPDN29
bits : 10 - 10 (1 bit)
access : read-write

INSEL29 : INSEL29
bits : 12 - 14 (3 bit)
access : read-write

EN30 : EN30
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL30 : OUTSEL30
bits : 17 - 17 (1 bit)
access : read-write

UPDN30 : UPDN30
bits : 18 - 18 (1 bit)
access : read-write

INSEL30 : INSEL30
bits : 20 - 22 (3 bit)
access : read-write

EN31 : EN31
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL31 : OUTSEL31
bits : 25 - 25 (1 bit)
access : read-write

UPDN31 : UPDN31
bits : 26 - 26 (1 bit)
access : read-write

INSEL31 : INSEL31
bits : 28 - 30 (3 bit)
access : read-write


CR8

TRGSEL Control register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR8 CR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN32 OUTSEL32 UPDN32 INSEL32 EN33 OUTSEL33 UPDN33 INSEL33 EN34 OUTSEL34 UPDN34 INSEL34 EN35 OUTSEL35 UPDN35 INSEL35

EN32 : EN32
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL32 : OUTSEL32
bits : 1 - 1 (1 bit)
access : read-write

UPDN32 : UPDN32
bits : 2 - 2 (1 bit)
access : read-write

INSEL32 : INSEL32
bits : 4 - 6 (3 bit)
access : read-write

EN33 : EN33
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL33 : OUTSEL33
bits : 9 - 9 (1 bit)
access : read-write

UPDN33 : UPDN33
bits : 10 - 10 (1 bit)
access : read-write

INSEL33 : INSEL33
bits : 12 - 14 (3 bit)
access : read-write

EN34 : EN34
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL34 : OUTSEL34
bits : 17 - 17 (1 bit)
access : read-write

UPDN34 : UPDN34
bits : 18 - 18 (1 bit)
access : read-write

INSEL34 : INSEL34
bits : 20 - 22 (3 bit)
access : read-write

EN35 : EN35
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL35 : OUTSEL35
bits : 25 - 25 (1 bit)
access : read-write

UPDN35 : UPDN35
bits : 26 - 26 (1 bit)
access : read-write

INSEL35 : INSEL35
bits : 28 - 30 (3 bit)
access : read-write


CR9

TRGSEL Control register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR9 CR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN36 OUTSEL36 UPDN36 INSEL36 EN37 OUTSEL37 UPDN37 INSEL37 EN38 OUTSEL38 UPDN38 INSEL38 EN39 OUTSEL39 UPDN39 INSEL39

EN36 : EN36
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL36 : OUTSEL36
bits : 1 - 1 (1 bit)
access : read-write

UPDN36 : UPDN36
bits : 2 - 2 (1 bit)
access : read-write

INSEL36 : INSEL36
bits : 4 - 6 (3 bit)
access : read-write

EN37 : EN37
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL37 : OUTSEL37
bits : 9 - 9 (1 bit)
access : read-write

UPDN37 : UPDN37
bits : 10 - 10 (1 bit)
access : read-write

INSEL37 : INSEL37
bits : 12 - 14 (3 bit)
access : read-write

EN38 : EN38
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL38 : OUTSEL38
bits : 17 - 17 (1 bit)
access : read-write

UPDN38 : UPDN38
bits : 18 - 18 (1 bit)
access : read-write

INSEL38 : INSEL38
bits : 20 - 22 (3 bit)
access : read-write

EN39 : EN39
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL39 : OUTSEL39
bits : 25 - 25 (1 bit)
access : read-write

UPDN39 : UPDN39
bits : 26 - 26 (1 bit)
access : read-write

INSEL39 : INSEL39
bits : 28 - 30 (3 bit)
access : read-write


CR10

TRGSEL Control register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR10 CR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN40 OUTSEL40 UPDN40 INSEL40 EN41 OUTSEL41 UPDN41 INSEL41 EN42 OUTSEL42 UPDN42 INSEL42 EN43 OUTSEL43 UPDN43 INSEL43

EN40 : EN40
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL40 : OUTSEL40
bits : 1 - 1 (1 bit)
access : read-write

UPDN40 : UPDN40
bits : 2 - 2 (1 bit)
access : read-write

INSEL40 : INSEL40
bits : 4 - 6 (3 bit)
access : read-write

EN41 : EN41
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL41 : OUTSEL41
bits : 9 - 9 (1 bit)
access : read-write

UPDN41 : UPDN41
bits : 10 - 10 (1 bit)
access : read-write

INSEL41 : INSEL41
bits : 12 - 14 (3 bit)
access : read-write

EN42 : EN42
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL42 : OUTSEL42
bits : 17 - 17 (1 bit)
access : read-write

UPDN42 : UPDN42
bits : 18 - 18 (1 bit)
access : read-write

INSEL42 : INSEL42
bits : 20 - 22 (3 bit)
access : read-write

EN43 : EN43
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL43 : OUTSEL43
bits : 25 - 25 (1 bit)
access : read-write

UPDN43 : UPDN43
bits : 26 - 26 (1 bit)
access : read-write

INSEL43 : INSEL43
bits : 28 - 30 (3 bit)
access : read-write


CR11

TRGSEL Control register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR11 CR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN44 OUTSEL44 UPDN44 INSEL44 EN45 OUTSEL45 UPDN45 INSEL45 EN46 OUTSEL46 UPDN46 INSEL46 EN47 OUTSEL47 UPDN47 INSEL47

EN44 : EN44
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL44 : OUTSEL44
bits : 1 - 1 (1 bit)
access : read-write

UPDN44 : UPDN44
bits : 2 - 2 (1 bit)
access : read-write

INSEL44 : INSEL44
bits : 4 - 6 (3 bit)
access : read-write

EN45 : EN45
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL45 : OUTSEL45
bits : 9 - 9 (1 bit)
access : read-write

UPDN45 : UPDN45
bits : 10 - 10 (1 bit)
access : read-write

INSEL45 : INSEL45
bits : 12 - 14 (3 bit)
access : read-write

EN46 : EN46
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL46 : OUTSEL46
bits : 17 - 17 (1 bit)
access : read-write

UPDN46 : UPDN46
bits : 18 - 18 (1 bit)
access : read-write

INSEL46 : INSEL46
bits : 20 - 22 (3 bit)
access : read-write

EN47 : EN47
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL47 : OUTSEL47
bits : 25 - 25 (1 bit)
access : read-write

UPDN47 : UPDN47
bits : 26 - 26 (1 bit)
access : read-write

INSEL47 : INSEL47
bits : 28 - 30 (3 bit)
access : read-write


CR12

TRGSEL Control register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR12 CR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN48 OUTSEL48 UPDN48 INSEL48 EN49 OUTSEL49 UPDN49 INSEL49 EN50 OUTSEL50 UPDN50 INSEL50 EN51 OUTSEL51 UPDN51 INSEL51

EN48 : EN48
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL48 : OUTSEL48
bits : 1 - 1 (1 bit)
access : read-write

UPDN48 : UPDN48
bits : 2 - 2 (1 bit)
access : read-write

INSEL48 : INSEL48
bits : 4 - 6 (3 bit)
access : read-write

EN49 : EN49
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL49 : OUTSEL49
bits : 9 - 9 (1 bit)
access : read-write

UPDN49 : UPDN49
bits : 10 - 10 (1 bit)
access : read-write

INSEL49 : INSEL49
bits : 12 - 14 (3 bit)
access : read-write

EN50 : EN50
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL50 : OUTSEL50
bits : 17 - 17 (1 bit)
access : read-write

UPDN50 : UPDN50
bits : 18 - 18 (1 bit)
access : read-write

INSEL50 : INSEL50
bits : 20 - 22 (3 bit)
access : read-write

EN51 : EN51
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL51 : OUTSEL51
bits : 25 - 25 (1 bit)
access : read-write

UPDN51 : UPDN51
bits : 26 - 26 (1 bit)
access : read-write

INSEL51 : INSEL51
bits : 28 - 30 (3 bit)
access : read-write


CR13

TRGSEL Control register 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR13 CR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN52 OUTSEL52 UPDN52 INSEL52 EN53 OUTSEL53 UPDN53 INSEL53 EN54 OUTSEL54 UPDN54 INSEL54 EN55 OUTSEL55 UPDN55 INSEL55

EN52 : EN52
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL52 : OUTSEL52
bits : 1 - 1 (1 bit)
access : read-write

UPDN52 : UPDN52
bits : 2 - 2 (1 bit)
access : read-write

INSEL52 : INSEL52
bits : 4 - 6 (3 bit)
access : read-write

EN53 : EN53
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL53 : OUTSEL53
bits : 9 - 9 (1 bit)
access : read-write

UPDN53 : UPDN53
bits : 10 - 10 (1 bit)
access : read-write

INSEL53 : INSEL53
bits : 12 - 14 (3 bit)
access : read-write

EN54 : EN54
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL54 : OUTSEL54
bits : 17 - 17 (1 bit)
access : read-write

UPDN54 : UPDN54
bits : 18 - 18 (1 bit)
access : read-write

INSEL54 : INSEL54
bits : 20 - 22 (3 bit)
access : read-write

EN55 : EN55
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL55 : OUTSEL55
bits : 25 - 25 (1 bit)
access : read-write

UPDN55 : UPDN55
bits : 26 - 26 (1 bit)
access : read-write

INSEL55 : INSEL55
bits : 28 - 30 (3 bit)
access : read-write


CR14

TRGSEL Control register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR14 CR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN56 OUTSEL56 UPDN56 INSEL56 EN57 OUTSEL57 UPDN57 INSEL57 EN58 OUTSEL58 UPDN58 INSEL58 EN59 OUTSEL59 UPDN59 INSEL59

EN56 : EN56
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL56 : OUTSEL56
bits : 1 - 1 (1 bit)
access : read-write

UPDN56 : UPDN56
bits : 2 - 2 (1 bit)
access : read-write

INSEL56 : INSEL56
bits : 4 - 6 (3 bit)
access : read-write

EN57 : EN57
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL57 : OUTSEL57
bits : 9 - 9 (1 bit)
access : read-write

UPDN57 : UPDN57
bits : 10 - 10 (1 bit)
access : read-write

INSEL57 : INSEL57
bits : 12 - 14 (3 bit)
access : read-write

EN58 : EN58
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL58 : OUTSEL58
bits : 17 - 17 (1 bit)
access : read-write

UPDN58 : UPDN58
bits : 18 - 18 (1 bit)
access : read-write

INSEL58 : INSEL58
bits : 20 - 22 (3 bit)
access : read-write

EN59 : EN59
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL59 : OUTSEL59
bits : 25 - 25 (1 bit)
access : read-write

UPDN59 : UPDN59
bits : 26 - 26 (1 bit)
access : read-write

INSEL59 : INSEL59
bits : 28 - 30 (3 bit)
access : read-write


CR15

TRGSEL Control register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR15 CR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN60 OUTSEL60 UPDN60 INSEL60 EN61 OUTSEL61 UPDN61 INSEL61 EN62 OUTSEL62 UPDN62 INSEL62 EN63 OUTSEL63 UPDN63 INSEL63

EN60 : EN60
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL60 : OUTSEL60
bits : 1 - 1 (1 bit)
access : read-write

UPDN60 : UPDN60
bits : 2 - 2 (1 bit)
access : read-write

INSEL60 : INSEL60
bits : 4 - 6 (3 bit)
access : read-write

EN61 : EN61
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL61 : OUTSEL61
bits : 9 - 9 (1 bit)
access : read-write

UPDN61 : UPDN61
bits : 10 - 10 (1 bit)
access : read-write

INSEL61 : INSEL61
bits : 12 - 14 (3 bit)
access : read-write

EN62 : EN62
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL62 : OUTSEL62
bits : 17 - 17 (1 bit)
access : read-write

UPDN62 : UPDN62
bits : 18 - 18 (1 bit)
access : read-write

INSEL62 : INSEL62
bits : 20 - 22 (3 bit)
access : read-write

EN63 : EN63
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL63 : OUTSEL63
bits : 25 - 25 (1 bit)
access : read-write

UPDN63 : UPDN63
bits : 26 - 26 (1 bit)
access : read-write

INSEL63 : INSEL63
bits : 28 - 30 (3 bit)
access : read-write


CR1

TRGSEL Control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN4 OUTSEL4 UPDN4 INSEL4 EN5 OUTSEL5 UPDN5 INSEL5 EN6 OUTSEL6 UPDN6 INSEL6 EN7 OUTSEL7 UPDN7 INSEL7

EN4 : EN4
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL4 : OUTSEL4
bits : 1 - 1 (1 bit)
access : read-write

UPDN4 : UPDN4
bits : 2 - 2 (1 bit)
access : read-write

INSEL4 : INSEL4
bits : 4 - 6 (3 bit)
access : read-write

EN5 : EN5
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL5 : OUTSEL5
bits : 9 - 9 (1 bit)
access : read-write

UPDN5 : UPDN5
bits : 10 - 10 (1 bit)
access : read-write

INSEL5 : INSEL5
bits : 12 - 14 (3 bit)
access : read-write

EN6 : EN6
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL6 : OUTSEL6
bits : 17 - 17 (1 bit)
access : read-write

UPDN6 : UPDN6
bits : 18 - 18 (1 bit)
access : read-write

INSEL6 : INSEL6
bits : 20 - 22 (3 bit)
access : read-write

EN7 : EN7
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL7 : OUTSEL7
bits : 25 - 25 (1 bit)
access : read-write

UPDN7 : UPDN7
bits : 26 - 26 (1 bit)
access : read-write

INSEL7 : INSEL7
bits : 28 - 30 (3 bit)
access : read-write


CR2

TSEL Control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN8 OUTSEL8 UPDN8 INSEL8 EN9 OUTSEL9 UPDN9 INSEL9 EN10 OUTSEL10 UPDN10 INSEL10 EN11 OUTSEL11 UPDN11 INSEL11

EN8 : EN8
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL8 : OUTSEL8
bits : 1 - 1 (1 bit)
access : read-write

UPDN8 : UPDN8
bits : 2 - 2 (1 bit)
access : read-write

INSEL8 : INSEL8
bits : 4 - 6 (3 bit)
access : read-write

EN9 : EN9
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL9 : OUTSEL9
bits : 9 - 9 (1 bit)
access : read-write

UPDN9 : UPDN9
bits : 10 - 10 (1 bit)
access : read-write

INSEL9 : INSEL9
bits : 12 - 14 (3 bit)
access : read-write

EN10 : EN10
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL10 : OUTSEL10
bits : 17 - 17 (1 bit)
access : read-write

UPDN10 : UPDN10
bits : 18 - 18 (1 bit)
access : read-write

INSEL10 : INSEL10
bits : 20 - 22 (3 bit)
access : read-write

EN11 : EN11
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL11 : OUTSEL11
bits : 25 - 25 (1 bit)
access : read-write

UPDN11 : UPDN11
bits : 26 - 26 (1 bit)
access : read-write

INSEL11 : INSEL11
bits : 28 - 30 (3 bit)
access : read-write


CR3

TRGSEL Control register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN12 OUTSEL12 UPDN12 INSEL12 EN13 OUTSEL13 UPDN13 INSEL13 EN14 OUTSEL14 UPDN14 INSEL14 EN15 OUTSEL15 UPDN15 INSEL15

EN12 : EN12
bits : 0 - 0 (1 bit)
access : read-write

OUTSEL12 : OUTSEL12
bits : 1 - 1 (1 bit)
access : read-write

UPDN12 : UPDN12
bits : 2 - 2 (1 bit)
access : read-write

INSEL12 : INSEL12
bits : 4 - 6 (3 bit)
access : read-write

EN13 : EN13
bits : 8 - 8 (1 bit)
access : read-write

OUTSEL13 : OUTSEL13
bits : 9 - 9 (1 bit)
access : read-write

UPDN13 : UPDN13
bits : 10 - 10 (1 bit)
access : read-write

INSEL13 : INSEL13
bits : 12 - 14 (3 bit)
access : read-write

EN14 : EN14
bits : 16 - 16 (1 bit)
access : read-write

OUTSEL14 : OUTSEL14
bits : 17 - 17 (1 bit)
access : read-write

UPDN14 : UPDN14
bits : 18 - 18 (1 bit)
access : read-write

INSEL14 : INSEL14
bits : 20 - 22 (3 bit)
access : read-write

EN15 : EN15
bits : 24 - 24 (1 bit)
access : read-write

OUTSEL15 : OUTSEL15
bits : 25 - 25 (1 bit)
access : read-write

UPDN15 : UPDN15
bits : 26 - 26 (1 bit)
access : read-write

INSEL15 : INSEL15
bits : 28 - 30 (3 bit)
access : read-write



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