\n

RPAR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTL

EAD1

EAD2

EAD3

ST

CLR

EAD0


CTL

RAMM Parity control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPAREN RPARF

RPAREN : RPAREN
bits : 0 - 0 (1 bit)
access : read-write

RPARF : RPARF
bits : 1 - 1 (1 bit)
access : read-write


EAD1

RAMM Parity Error address register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EAD1 EAD1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPAREADD1

RPAREADD1 : RPAREADD1
bits : 0 - 31 (32 bit)
access : read-only


EAD2

RAMM Parity Error address register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EAD2 EAD2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPAREADD2

RPAREADD2 : RPAREADD2
bits : 0 - 31 (32 bit)
access : read-only


EAD3

RAMM Parity Error address register 3
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EAD3 EAD3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPAREADD3

RPAREADD3 : RPAREADD3
bits : 0 - 31 (32 bit)
access : read-only


ST

RAMM Parity status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ST ST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPARFG0 RPARFG1 RPARFG2 RPARFG3

RPARFG0 : RPARFG0
bits : 0 - 0 (1 bit)
access : read-only

RPARFG1 : RPARFG1
bits : 1 - 1 (1 bit)
access : read-only

RPARFG2 : RPARFG2
bits : 2 - 2 (1 bit)
access : read-only

RPARFG3 : RPARFG3
bits : 3 - 3 (1 bit)
access : read-only


CLR

RAMM Parity status clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CLR CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPARCLR0 RPARCLR1 RPARCLR2 RPARCLR3

RPARCLR0 : RPARCLR0
bits : 0 - 0 (1 bit)
access : write-only

RPARCLR1 : RPARCLR1
bits : 1 - 1 (1 bit)
access : write-only

RPARCLR2 : RPARCLR2
bits : 2 - 2 (1 bit)
access : write-only

RPARCLR3 : RPARCLR3
bits : 3 - 3 (1 bit)
access : write-only


EAD0

RAMM Parity Error address register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EAD0 EAD0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPAREADD0

RPAREADD0 : RPAREADD0
bits : 0 - 31 (32 bit)
access : read-only



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