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CG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

PROTECT

SCOCR

PLL0SEL

WUPHCR

WUPLCR

OSCCR

FSYSENA

FSYSENB

FCEN

SPCLKEN

SYSCR

STBYCR


PROTECT

CG Protect Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTECT PROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT

PROTECT : PROTECT
bits : 0 - 7 (8 bit)
access : read-write


SCOCR

CG SCOUT Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCOCR SCOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCOEN SCOSEL SCODIV

SCOEN : SCOEN
bits : 0 - 0 (1 bit)
access : read-write

SCOSEL : SCOSEL
bits : 1 - 3 (3 bit)
access : read-write

SCODIV : SCODIV
bits : 4 - 6 (3 bit)
access : read-write


PLL0SEL

CG PLL select register for fsys
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL0SEL PLL0SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL0ON PLL0SEL PLL0ST PLL0SET

PLL0ON : PLL0ON
bits : 0 - 0 (1 bit)
access : read-write

PLL0SEL : PLL0SEL
bits : 1 - 1 (1 bit)
access : read-write

PLL0ST : PLL0ST
bits : 2 - 2 (1 bit)
access : read-only

PLL0SET : PLL0SET
bits : 8 - 31 (24 bit)
access : read-write


WUPHCR

CG Warmup register for HOSC
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUPHCR WUPHCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUON WUEF WUCLK WUPT

WUON : WUON
bits : 0 - 0 (1 bit)
access : write-only

WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only

WUCLK : WUCLK
bits : 8 - 8 (1 bit)
access : read-write

WUPT : WUPT
bits : 20 - 31 (12 bit)
access : read-write


WUPLCR

CG Low-speed oscillation warm-up register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUPLCR WUPLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WULON WULEF WUPTL

WULON : WULON
bits : 0 - 0 (1 bit)
access : write-only

WULEF : WULEF
bits : 1 - 1 (1 bit)
access : read-only

WUPTL : WUPTL
bits : 12 - 26 (15 bit)
access : read-write


OSCCR

CG Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCR OSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IHOSC1EN EOSCEN IHOSC2EN OSCSEL OSCF IHOSC1F IHOSC2F

IHOSC1EN : IHOSC1EN
bits : 0 - 0 (1 bit)
access : read-write

EOSCEN : EOSCEN
bits : 1 - 2 (2 bit)
access : read-write

IHOSC2EN : IHOSC2EN
bits : 3 - 3 (1 bit)
access : read-write

OSCSEL : OSCSEL
bits : 8 - 8 (1 bit)
access : read-write

OSCF : OSCF
bits : 9 - 9 (1 bit)
access : read-only

IHOSC1F : IHOSC1F
bits : 16 - 16 (1 bit)
access : read-only

IHOSC2F : IHOSC2F
bits : 19 - 19 (1 bit)
access : read-only


FSYSENA

CG output control register A for fsys clock
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYSENA FSYSENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPENA00 IPENA01 IPENA02 IPENA03 IPENA04 IPENA05 IPENA06 IPENA07 IPENA08 IPENA09 IPENA10 IPENA11 IPENA12 IPENA13 IPENA14 IPENA17 IPENA18 IPENA19 IPENA20 IPENA21 IPENA22 IPENA23 IPENA24 IPENA25 IPENA26 IPENA27 IPENA28 IPENA29 IPENA30 IPENA31

IPENA00 : IPENA00
bits : 0 - 0 (1 bit)
access : read-write

IPENA01 : IPENA01
bits : 1 - 1 (1 bit)
access : read-write

IPENA02 : IPENA02
bits : 2 - 2 (1 bit)
access : read-write

IPENA03 : IPENA03
bits : 3 - 3 (1 bit)
access : read-write

IPENA04 : IPENA04
bits : 4 - 4 (1 bit)
access : read-write

IPENA05 : IPENA05
bits : 5 - 5 (1 bit)
access : read-write

IPENA06 : IPENA06
bits : 6 - 6 (1 bit)
access : read-write

IPENA07 : IPENA07
bits : 7 - 7 (1 bit)
access : read-write

IPENA08 : IPENA08
bits : 8 - 8 (1 bit)
access : read-write

IPENA09 : IPENA09
bits : 9 - 9 (1 bit)
access : read-write

IPENA10 : IPENA10
bits : 10 - 10 (1 bit)
access : read-write

IPENA11 : IPENA11
bits : 11 - 11 (1 bit)
access : read-write

IPENA12 : IPENA12
bits : 12 - 12 (1 bit)
access : read-write

IPENA13 : IPENA13
bits : 13 - 13 (1 bit)
access : read-write

IPENA14 : IPENA14
bits : 14 - 14 (1 bit)
access : read-write

IPENA17 : IPENA17
bits : 17 - 17 (1 bit)
access : read-write

IPENA18 : IPENA18
bits : 18 - 18 (1 bit)
access : read-write

IPENA19 : IPENA19
bits : 19 - 19 (1 bit)
access : read-write

IPENA20 : IPENA20
bits : 20 - 20 (1 bit)
access : read-write

IPENA21 : IPENA21
bits : 21 - 21 (1 bit)
access : read-write

IPENA22 : IPENA22
bits : 22 - 22 (1 bit)
access : read-write

IPENA23 : IPENA23
bits : 23 - 23 (1 bit)
access : read-write

IPENA24 : IPENA24
bits : 24 - 24 (1 bit)
access : read-write

IPENA25 : IPENA25
bits : 25 - 25 (1 bit)
access : read-write

IPENA26 : IPENA26
bits : 26 - 26 (1 bit)
access : read-write

IPENA27 : IPENA27
bits : 27 - 27 (1 bit)
access : read-write

IPENA28 : IPENA28
bits : 28 - 28 (1 bit)
access : read-write

IPENA29 : IPENA29
bits : 29 - 29 (1 bit)
access : read-write

IPENA30 : IPENA30
bits : 30 - 30 (1 bit)
access : read-write

IPENA31 : IPENA31
bits : 31 - 31 (1 bit)
access : read-write


FSYSENB

CG output control register B for fsys clock
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYSENB FSYSENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPENB00 IPENB01 IPENB02 IPENB03 IPENB05 IPENB06 IPENB07 IPENB08 IPENB09 IPENB10 IPENB11 IPENB12 IPENB13 IPENB15 IPENB16 IPENB17 IPENB18 IPENB19 IPENB20 IPENB21 IPENB22 IPENB23 IPENB31

IPENB00 : IPENB00
bits : 0 - 0 (1 bit)
access : read-write

IPENB01 : IPENB01
bits : 1 - 1 (1 bit)
access : read-write

IPENB02 : IPENB02
bits : 2 - 2 (1 bit)
access : read-write

IPENB03 : IPENB03
bits : 3 - 3 (1 bit)
access : read-write

IPENB05 : IPENB05
bits : 5 - 5 (1 bit)
access : read-write

IPENB06 : IPENB06
bits : 6 - 6 (1 bit)
access : read-write

IPENB07 : IPENB07
bits : 7 - 7 (1 bit)
access : read-write

IPENB08 : IPENB08
bits : 8 - 8 (1 bit)
access : read-write

IPENB09 : IPENB09
bits : 9 - 9 (1 bit)
access : read-write

IPENB10 : IPENB10
bits : 10 - 10 (1 bit)
access : read-write

IPENB11 : IPENB11
bits : 11 - 11 (1 bit)
access : read-write

IPENB12 : IPENB12
bits : 12 - 12 (1 bit)
access : read-write

IPENB13 : IPENB13
bits : 13 - 13 (1 bit)
access : read-write

IPENB15 : IPENB15
bits : 15 - 15 (1 bit)
access : read-write

IPENB16 : IPENB16
bits : 16 - 16 (1 bit)
access : read-write

IPENB17 : IPENB17
bits : 17 - 17 (1 bit)
access : read-write

IPENB18 : IPENB18
bits : 18 - 18 (1 bit)
access : read-write

IPENB19 : IPENB19
bits : 19 - 19 (1 bit)
access : read-write

IPENB20 : IPENB20
bits : 20 - 20 (1 bit)
access : read-write

IPENB21 : IPENB21
bits : 21 - 21 (1 bit)
access : read-write

IPENB22 : IPENB22
bits : 22 - 22 (1 bit)
access : read-write

IPENB23 : IPENB23
bits : 23 - 23 (1 bit)
access : read-write

IPENB31 : IPENB31
bits : 31 - 31 (1 bit)
access : read-write


FCEN

CG output control register for fc clock
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCEN FCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCIPEN07

FCIPEN07 : FCIPEN07
bits : 7 - 7 (1 bit)
access : read-write


SPCLKEN

CG Output control register for ADC AND TRACE CLOCK
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCLKEN SPCLKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCKEN ADCKEN

TRCKEN : TRCKEN
bits : 0 - 0 (1 bit)
access : read-write

ADCKEN : ADCKEN
bits : 16 - 16 (1 bit)
access : read-write


SYSCR

CG System clock control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCR SYSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEAR PRCK GEARST PRCKST

GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write

PRCK : PRCK
bits : 8 - 11 (4 bit)
access : read-write

GEARST : GEARST
bits : 16 - 18 (3 bit)
access : read-only

PRCKST : PRCKST
bits : 24 - 27 (4 bit)
access : read-only


STBYCR

CG Standby Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STBYCR STBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY

STBY : STBY
bits : 0 - 1 (2 bit)
access : read-write



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