\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0xCC byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x114 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
DMAC Interrupt Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTSTATUS0 : INTSTATUS0
bits : 0 - 0 (1 bit)
access : read-only
INTSTATUS1 : INTSTATUS1
bits : 1 - 1 (1 bit)
access : read-only
DMAC Interrupt Error Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTERRCLR0 : INTERRCLR0
bits : 0 - 0 (1 bit)
access : write-only
INTERRCLR1 : INTERRCLR1
bits : 1 - 1 (1 bit)
access : write-only
DMAC Channel0 Source Address Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : SRCADDR
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel0 Destination Address Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DESTADDR : DESTADDR
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel0 Linked List Item Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : LLI
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel0 Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRANSFERSIZE : TRANSFERSIZE
bits : 0 - 11 (12 bit)
access : read-write
SBSIZE : SBSIZE
bits : 12 - 14 (3 bit)
access : read-write
DBSIZE : DBSIZE
bits : 15 - 17 (3 bit)
access : read-write
SWIDTH : SWIDTH
bits : 18 - 20 (3 bit)
access : read-write
DWIDTH : DWIDTH
bits : 21 - 23 (3 bit)
access : read-write
SI : SI
bits : 26 - 26 (1 bit)
access : read-write
DI : DI
bits : 27 - 27 (1 bit)
access : read-write
I : I
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel0 Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : E
bits : 0 - 0 (1 bit)
access : read-write
SRCPERIPHERAL : SRCPERIPHERAL
bits : 1 - 4 (4 bit)
access : read-write
DESTPERIPHERAL : DESTPERIPHERAL
bits : 6 - 9 (4 bit)
access : read-write
FLOWCNTRL : FLOWCNTRL
bits : 11 - 13 (3 bit)
access : read-write
IE : IE
bits : 14 - 14 (1 bit)
access : read-write
ITC : ITC
bits : 15 - 15 (1 bit)
access : read-write
LOCK : LOCK
bits : 16 - 16 (1 bit)
access : read-write
ACTIVE : ACTIVE
bits : 17 - 17 (1 bit)
access : read-only
HALT : HALT
bits : 18 - 18 (1 bit)
access : read-write
DMAC Channel1 Source Address Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : SRCADDR
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel1 Destination Address Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DESTADDR : DESTADDR
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel1 Linked List Item Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : LLI
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel1Control Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRANSFERSIZE : TRANSFERSIZE
bits : 0 - 11 (12 bit)
access : read-write
SBSIZE : SBSIZE
bits : 12 - 14 (3 bit)
access : read-write
DBSIZE : DBSIZE
bits : 15 - 17 (3 bit)
access : read-write
SWIDTH : SWIDTH
bits : 18 - 20 (3 bit)
access : read-write
DWIDTH : DWIDTH
bits : 21 - 23 (3 bit)
access : read-write
SI : SI
bits : 26 - 26 (1 bit)
access : read-write
DI : DI
bits : 27 - 27 (1 bit)
access : read-write
I : I
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel1 Configuration Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : E
bits : 0 - 0 (1 bit)
access : read-write
SRCPERIPHERAL : SRCPERIPHERAL
bits : 1 - 4 (4 bit)
access : read-write
DESTPERIPHERAL : DESTPERIPHERAL
bits : 6 - 9 (4 bit)
access : read-write
FLOWCNTRL : FLOWCNTRL
bits : 11 - 13 (3 bit)
access : read-write
IE : IE
bits : 14 - 14 (1 bit)
access : read-write
ITC : ITC
bits : 15 - 15 (1 bit)
access : read-write
LOCK : LOCK
bits : 16 - 16 (1 bit)
access : read-write
ACTIVE : ACTIVE
bits : 17 - 17 (1 bit)
access : read-only
HALT : HALT
bits : 18 - 18 (1 bit)
access : read-write
DMAC Raw Interrupt Terminal Count Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAWINTTCS0 : RAWINTTCS0
bits : 0 - 0 (1 bit)
access : read-only
RAWINTTCS1 : RAWINTTCS1
bits : 1 - 1 (1 bit)
access : read-only
DMAC Raw Error Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAWINTERRS0 : RAWINTERRS0
bits : 0 - 0 (1 bit)
access : read-only
RAWINTERRS1 : RAWINTERRS1
bits : 1 - 1 (1 bit)
access : read-only
DMAC Enabled Channel Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLEDCH0 : ENABLEDCH0
bits : 0 - 0 (1 bit)
access : read-only
ENABLEDCH1 : ENABLEDCH1
bits : 1 - 1 (1 bit)
access : read-only
DMAC Software Burst Request Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFTBREQ0 : SOFTBREQ0
bits : 0 - 0 (1 bit)
access : read-write
SOFTBREQ1 : SOFTBREQ1
bits : 1 - 1 (1 bit)
access : read-write
SOFTBREQ2 : SOFTBREQ2
bits : 2 - 2 (1 bit)
access : read-write
SOFTBREQ3 : SOFTBREQ3
bits : 3 - 3 (1 bit)
access : read-write
SOFTBREQ4 : SOFTBREQ4
bits : 4 - 4 (1 bit)
access : read-write
SOFTBREQ5 : SOFTBREQ5
bits : 5 - 5 (1 bit)
access : read-write
SOFTBREQ6 : SOFTBREQ6
bits : 6 - 6 (1 bit)
access : read-write
SOFTBREQ7 : SOFTBREQ7
bits : 7 - 7 (1 bit)
access : read-write
SOFTBREQ8 : SOFTBREQ8
bits : 8 - 8 (1 bit)
access : read-write
DMAC Software Single Request Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFTSREQ6 : SOFTSREQ6
bits : 6 - 6 (1 bit)
access : read-write
SOFTSREQ8 : SOFTSREQ8
bits : 8 - 8 (1 bit)
access : read-write
DMAC Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : E
bits : 0 - 0 (1 bit)
access : read-write
M : M
bits : 1 - 1 (1 bit)
access : read-write
DMAC Interrupt Terminal Count Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTTCSTATUS0 : INTTCSTATUS0
bits : 0 - 0 (1 bit)
access : read-only
INTTCSTATUS1 : INTTCSTATUS1
bits : 1 - 1 (1 bit)
access : read-only
DMAC Interrupt Terminal Count Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTTCCLEAR0 : INTTCCLEAR0
bits : 0 - 0 (1 bit)
access : write-only
INTTCCLEAR1 : INTTCCLEAR1
bits : 1 - 1 (1 bit)
access : write-only
DMAC Interrupt Error Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTERRSTATUS0 : INTERRSTATUS0
bits : 0 - 0 (1 bit)
access : read-only
INTERRSTATUS1 : INTERRSTATUS1
bits : 1 - 1 (1 bit)
access : read-only
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