\n
address_offset : 0x0 Bytes (0x0)
size : 0x7 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x7 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x7 byte (0x0)
mem_usage : registers
protection : not protected
Display Selection Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : MODE
bits : 0 - 0 (1 bit)
access : read-write
Configuration Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLF : SLF
bits : 1 - 2 (2 bit)
access : read-write
DUTY : DUTY
bits : 3 - 4 (2 bit)
access : read-write
VFSEL : VFSEL
bits : 5 - 6 (2 bit)
access : read-write
CPEN : CPEN
bits : 7 - 7 (1 bit)
access : read-write
Display Screen Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATANUM : DATANUM
bits : 0 - 6 (7 bit)
access : read-write
Total Display Time Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : TIMEOUT
bits : 0 - 6 (7 bit)
access : read-write
Screen Switch Time Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDATE : UPDATE
bits : 0 - 4 (5 bit)
access : read-write
Response Count Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISPNUM : DISPNUM
bits : 0 - 3 (4 bit)
access : read-write
Display Reponse Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESPNUM : RESPNUM
bits : 0 - 3 (4 bit)
access : read-write
Display Start Time Register (Second)
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC : SEC
bits : 0 - 6 (7 bit)
access : read-only
Display Start Time Register (Minutes)
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MIN : MIN
bits : 0 - 6 (7 bit)
access : read-only
Display Start Time Register (Hour)
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HOUR : HOUR
bits : 0 - 5 (6 bit)
access : read-only
HSEL : HSEL
bits : 6 - 6 (1 bit)
access : read-only
Display Start Time Register (Day)
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAY : DAY
bits : 0 - 5 (6 bit)
access : read-only
Display Start Time Register (Month)
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MONTH : MONTH
bits : 0 - 4 (5 bit)
access : read-only
Display Start Time Register (Year)
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
YEAR : YEAR
bits : 0 - 7 (8 bit)
access : read-only
Low-speec Clock Control Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRVOSCL : DRVOSCL
bits : 0 - 0 (1 bit)
access : read-write
AOCKSEL : AOCKSEL
bits : 1 - 1 (1 bit)
access : read-write
AOCKF : AOCKF
bits : 2 - 2 (1 bit)
access : read-only
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