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INT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR0

CR4

CR5

CR6

CR7

CR8

CR9

CR10

CR11

CR12

CR13

CR14

CR15

CR1

EN

CLR

RESETF

NMIF

RETF

LVDST

CR2

CR3


CR0

Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR4

Control Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR4 CR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR5

Control Register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR5 CR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR6

Control Register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR6 CR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR7

Control Register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR7 CR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR8

Control Register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR8 CR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR9

Control Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR9 CR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR10

Control Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR10 CR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR11

Control Register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR11 CR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR12

Control Register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR12 CR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR13

Control Register 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR13 CR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR14

Control Register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR14 CR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR15

Control Register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR15 CR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR1

Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


EN

STOP1 Mode Release Setting Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 EN8 EN9 EN10 EN11 EN12

EN0 : EN0
bits : 0 - 0 (1 bit)
access : read-write

EN1 : EN1
bits : 1 - 1 (1 bit)
access : read-write

EN2 : EN2
bits : 2 - 2 (1 bit)
access : read-write

EN3 : EN3
bits : 3 - 3 (1 bit)
access : read-write

EN4 : EN4
bits : 4 - 4 (1 bit)
access : read-write

EN5 : EN5
bits : 5 - 5 (1 bit)
access : read-write

EN6 : EN6
bits : 6 - 6 (1 bit)
access : read-write

EN7 : EN7
bits : 7 - 7 (1 bit)
access : read-write

EN8 : EN8
bits : 8 - 8 (1 bit)
access : read-write

EN9 : EN9
bits : 9 - 9 (1 bit)
access : read-write

EN10 : EN10
bits : 10 - 10 (1 bit)
access : read-write

EN11 : EN11
bits : 11 - 11 (1 bit)
access : read-write

EN12 : EN12
bits : 12 - 12 (1 bit)
access : read-write


CLR

Interrupt Request Clear Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CLR CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR

CLR : CLR
bits : 0 - 3 (4 bit)
access : write-only


RESETF

Reset Flag Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESETF RESETF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTF0 RSTF1 RSTF2 RSTF3 RSTF4

RSTF0 : RSTF0
bits : 0 - 0 (1 bit)
access : read-write

RSTF1 : RSTF1
bits : 1 - 1 (1 bit)
access : read-write

RSTF2 : RSTF2
bits : 2 - 2 (1 bit)
access : read-write

RSTF3 : RSTF3
bits : 3 - 3 (1 bit)
access : read-write

RSTF4 : RSTF4
bits : 4 - 4 (1 bit)
access : read-write


NMIF

NMI Flag Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMIF NMIF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIF0 NMIF1

NMIF0 : NMIF0
bits : 0 - 0 (1 bit)
access : read-only

NMIF1 : NMIF1
bits : 1 - 1 (1 bit)
access : read-only


RETF

STOP2_STOP3 Release Flag Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RETF RETF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RETF0 RETF1 RETF2 RETF3

RETF0 : RETF0
bits : 0 - 0 (1 bit)
access : read-write

RETF1 : RETF1
bits : 1 - 1 (1 bit)
access : read-write

RETF2 : RETF2
bits : 2 - 2 (1 bit)
access : read-write

RETF3 : RETF3
bits : 3 - 3 (1 bit)
access : read-write


LVDST

SD2 Area Voltage Status Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LVDST LVDST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDST

LVDST : LVDST
bits : 0 - 0 (1 bit)
access : read-only


CR2

Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only


CR3

Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT ST

ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write

ST : ST
bits : 4 - 5 (2 bit)
access : read-only



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