\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Control Regiser
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : INT
bits : 0 - 0 (1 bit)
access : read-write
Clock Control Register for Unit B
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CK : CK
bits : 0 - 0 (1 bit)
access : read-write
Reset Control Register for Unit B
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTREL : RSTREL
bits : 0 - 0 (1 bit)
access : read-write
Interrupt Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : CLR
bits : 0 - 0 (1 bit)
access : read-write
Transmit Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFOW : INFOW
bits : 0 - 31 (32 bit)
access : read-write
Receive Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INFOR : INFOR
bits : 0 - 31 (32 bit)
access : read-only
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