\n

PG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

PUP

IE

CR


DATA

Port G Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG0 PG1 PG2 PG3

PG0 : PG0
bits : 0 - 0 (1 bit)
access : read-write

PG1 : PG1
bits : 1 - 1 (1 bit)
access : read-write

PG2 : PG2
bits : 2 - 2 (1 bit)
access : read-write

PG3 : PG3
bits : 3 - 3 (1 bit)
access : read-write


PUP

Port G Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG0UP PG1UP PG2UP PG3UP

PG0UP : PG0UP
bits : 0 - 0 (1 bit)
access : read-write

PG1UP : PG1UP
bits : 1 - 1 (1 bit)
access : read-write

PG2UP : PG2UP
bits : 2 - 2 (1 bit)
access : read-write

PG3UP : PG3UP
bits : 3 - 3 (1 bit)
access : read-write


IE

Port G Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG0IE PG1IE PG2IE PG3IE

PG0IE : PG0IE
bits : 0 - 0 (1 bit)
access : read-write

PG1IE : PG1IE
bits : 1 - 1 (1 bit)
access : read-write

PG2IE : PG2IE
bits : 2 - 2 (1 bit)
access : read-write

PG3IE : PG3IE
bits : 3 - 3 (1 bit)
access : read-write


CR

Port G Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG0C PG1C PG2C PG3C

PG0C : PG0C
bits : 0 - 0 (1 bit)
access : read-write

PG1C : PG1C
bits : 1 - 1 (1 bit)
access : read-write

PG2C : PG2C
bits : 2 - 2 (1 bit)
access : read-write

PG3C : PG3C
bits : 3 - 3 (1 bit)
access : read-write



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