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address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
Protect Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGPROTECT : CGPROTECT
bits : 0 - 7 (8 bit)
access : read-write
Standby Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STBY : STBY
bits : 0 - 1 (2 bit)
access : read-write
Clock supply control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCA : ADCA
bits : 0 - 0 (1 bit)
access : read-write
DMACA : DMACA
bits : 1 - 1 (1 bit)
access : read-write
UART0 : UART0
bits : 2 - 2 (1 bit)
access : read-write
SSP0 : SSP0
bits : 3 - 3 (1 bit)
access : read-write
SSP1 : SSP1
bits : 4 - 4 (1 bit)
access : read-write
SSP2 : SSP2
bits : 5 - 5 (1 bit)
access : read-write
TRACECLK : TRACECLK
bits : 6 - 6 (1 bit)
access : read-write
Oscillation enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IHOSCEN : IHOSCEN
bits : 0 - 0 (1 bit)
access : read-write
EHOSCEN : EHOSCEN
bits : 1 - 2 (2 bit)
access : read-write
PLL setting Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSET : PLLSET
bits : 0 - 15 (16 bit)
access : read-write
PLL enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
High-speed oscillation warm-up Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUON : WUON
bits : 0 - 0 (1 bit)
access : write-only
WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only
WUCLK : WUCLK
bits : 8 - 8 (1 bit)
access : read-write
WUPT : WUPT
bits : 16 - 27 (12 bit)
access : read-write
Low-speed oscillation warm-up Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WULON : WULON
bits : 0 - 0 (1 bit)
access : write-only
WULEF : WULEF
bits : 1 - 1 (1 bit)
access : read-only
WUPTL : WUPTL
bits : 16 - 29 (14 bit)
access : read-write
SCOUT Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCOSEL : SCOSEL
bits : 0 - 2 (3 bit)
access : read-write
High-speed oscillation select Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSCSEL : OSCSEL
bits : 0 - 1 (2 bit)
access : read-write
High-speed oscillation status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OSCF : OSCF
bits : 0 - 1 (2 bit)
access : read-only
Clock Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write
PRCK : PRCK
bits : 3 - 5 (3 bit)
access : read-write
FPSEL : FPSEL
bits : 6 - 6 (1 bit)
access : read-write
STICK : STICK
bits : 7 - 7 (1 bit)
access : read-write
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