\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected
Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
STOP1 Mode Release Setting Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN0 : EN0
bits : 0 - 0 (1 bit)
access : read-write
EN1 : EN1
bits : 1 - 1 (1 bit)
access : read-write
EN2 : EN2
bits : 2 - 2 (1 bit)
access : read-write
EN3 : EN3
bits : 3 - 3 (1 bit)
access : read-write
EN4 : EN4
bits : 4 - 4 (1 bit)
access : read-write
EN5 : EN5
bits : 5 - 5 (1 bit)
access : read-write
EN6 : EN6
bits : 6 - 6 (1 bit)
access : read-write
EN7 : EN7
bits : 7 - 7 (1 bit)
access : read-write
Interrupt Request Clear Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : CLR
bits : 0 - 3 (4 bit)
access : write-only
Reset Flag Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTF3 : RSTF3
bits : 3 - 3 (1 bit)
access : read-write
RSTF4 : RSTF4
bits : 4 - 4 (1 bit)
access : read-write
RSTF5 : RSTF5
bits : 5 - 5 (1 bit)
access : read-write
NMI Flag Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMIF0 : NMIF0
bits : 0 - 0 (1 bit)
access : read-only
NMIF1 : NMIF1
bits : 1 - 1 (1 bit)
access : read-only
Peripheral Function Reset Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPRST0 : IPRST0
bits : 0 - 0 (1 bit)
access : read-write
IPRST1 : IPRST1
bits : 1 - 1 (1 bit)
access : read-write
IPRST2 : IPRST2
bits : 2 - 2 (1 bit)
access : read-write
IPRST3 : IPRST3
bits : 3 - 3 (1 bit)
access : read-write
Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : ACT
bits : 0 - 2 (3 bit)
access : read-write
ST : ST
bits : 4 - 5 (2 bit)
access : read-only
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