\n

PN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

PUP

IE

CR


DATA

Port N Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PN0 PN1 PN2 PN3 PN4

PN0 : PN0
bits : 0 - 0 (1 bit)
access : read-write

PN1 : PN1
bits : 1 - 1 (1 bit)
access : read-write

PN2 : PN2
bits : 2 - 2 (1 bit)
access : read-write

PN3 : PN3
bits : 3 - 3 (1 bit)
access : read-write

PN4 : PN4
bits : 4 - 4 (1 bit)
access : read-write


PUP

Port N Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PN0UP PN1UP PN2UP PN3UP PN4UP

PN0UP : PN0UP
bits : 0 - 0 (1 bit)
access : read-write

PN1UP : PN1UP
bits : 1 - 1 (1 bit)
access : read-write

PN2UP : PN2UP
bits : 2 - 2 (1 bit)
access : read-write

PN3UP : PN3UP
bits : 3 - 3 (1 bit)
access : read-write

PN4UP : PN4UP
bits : 4 - 4 (1 bit)
access : read-write


IE

Port N Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PN0IE PN1IE PN2IE PN3IE PN4IE

PN0IE : PN0IE
bits : 0 - 0 (1 bit)
access : read-write

PN1IE : PN1IE
bits : 1 - 1 (1 bit)
access : read-write

PN2IE : PN2IE
bits : 2 - 2 (1 bit)
access : read-write

PN3IE : PN3IE
bits : 3 - 3 (1 bit)
access : read-write

PN4IE : PN4IE
bits : 4 - 4 (1 bit)
access : read-write


CR

Port N Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PN0C PN1C PN2C PN3C PN4C

PN0C : PN0C
bits : 0 - 0 (1 bit)
access : read-write

PN1C : PN1C
bits : 1 - 1 (1 bit)
access : read-write

PN2C : PN2C
bits : 2 - 2 (1 bit)
access : read-write

PN3C : PN3C
bits : 3 - 3 (1 bit)
access : read-write

PN4C : PN4C
bits : 4 - 4 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.