\n

DMACNone

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

REDGE

RCLR


REDGE

DMAC Request Edge Setting Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REDGE REDGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEDGEA DEDGEB DEDGEC

DEDGEA : DEDGEA
bits : 0 - 0 (1 bit)
access : read-write

DEDGEB : DEDGEB
bits : 1 - 1 (1 bit)
access : read-write

DEDGEC : DEDGEC
bits : 2 - 2 (1 bit)
access : read-write


RCLR

DMAC Request Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RCLR RCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCLR0 DCLR1 DCLR2 DCLR8 DCLR9 DCLR16 DCLR17 DCLR18 DCLR19

DCLR0 : DCLR0
bits : 0 - 0 (1 bit)
access : write-only

DCLR1 : DCLR1
bits : 1 - 1 (1 bit)
access : write-only

DCLR2 : DCLR2
bits : 2 - 2 (1 bit)
access : read-only

DCLR8 : DCLR8
bits : 8 - 8 (1 bit)
access : write-only

DCLR9 : DCLR9
bits : 9 - 9 (1 bit)
access : write-only

DCLR16 : DCLR16
bits : 16 - 16 (1 bit)
access : write-only

DCLR17 : DCLR17
bits : 17 - 17 (1 bit)
access : write-only

DCLR18 : DCLR18
bits : 18 - 18 (1 bit)
access : write-only

DCLR19 : DCLR19
bits : 19 - 19 (1 bit)
access : write-only



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