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ESIO0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0xE4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x104 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : reserved
protection : not protected

Registers

CR0

BR

DR

FMTR0

FMTR1

SR

PERR

HPERR0

HPERR1

HPERR2

HPERR3

VPERR

CR1

CR2

CR3


CR0

ESIO Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESIOE SWRST

ESIOE : ESIOE
bits : 0 - 0 (1 bit)
access : read-write

SWRST : SWRST
bits : 6 - 7 (2 bit)
access : write-only


BR

ESIO Baud Rate Generator Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRS BRCK

BRS : BRS
bits : 0 - 3 (4 bit)
access : read-write

BRCK : BRCK
bits : 4 - 7 (4 bit)
access : read-write


DR

ESIO Data Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESIODR

ESIODR : ESIODR
bits : 0 - 30 (31 bit)
access : read-write


FMTR0

ESIO Format Control Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMTR0 FMTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCKCSDL CSSCKDL CS0POL CS1POL CSINT CKPOL FW FINT FL DIR

SCKCSDL : SCKCSDL
bits : 0 - 3 (4 bit)
access : read-write

CSSCKDL : CSSCKDL
bits : 4 - 7 (4 bit)
access : read-write

CS0POL : CS0POL
bits : 8 - 8 (1 bit)
access : read-write

CS1POL : CS1POL
bits : 9 - 9 (1 bit)
access : read-write

CSINT : CSINT
bits : 10 - 13 (4 bit)
access : read-write

CKPOL : CKPOL
bits : 14 - 14 (1 bit)
access : read-write

FW : FW
bits : 16 - 17 (2 bit)
access : read-write

FINT : FINT
bits : 20 - 23 (4 bit)
access : read-write

FL : FL
bits : 24 - 29 (6 bit)
access : read-write

DIR : DIR
bits : 31 - 31 (1 bit)
access : read-write


FMTR1

ESIO Format Control Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMTR1 FMTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPM VPE HPM HPE

VPM : VPM
bits : 0 - 0 (1 bit)
access : read-write

VPE : VPE
bits : 1 - 1 (1 bit)
access : read-write

HPM : HPM
bits : 2 - 2 (1 bit)
access : read-write

HPE : HPE
bits : 3 - 3 (1 bit)
access : read-write


SR

ESIO Status Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLVL RFFLL INTRXFF RWEND RXRUN TLVL TFEMP INTTXFF TWEND TXRUN ESIOSUE

RLVL : RLVL
bits : 0 - 3 (4 bit)
access : read-only

RFFLL : RFFLL
bits : 4 - 4 (1 bit)
access : read-only

INTRXFF : INTRXFF
bits : 5 - 5 (1 bit)
access : read-write

RWEND : RWEND
bits : 6 - 6 (1 bit)
access : read-write

RXRUN : RXRUN
bits : 7 - 7 (1 bit)
access : read-only

TLVL : TLVL
bits : 16 - 19 (4 bit)
access : read-only

TFEMP : TFEMP
bits : 20 - 20 (1 bit)
access : read-only

INTTXFF : INTTXFF
bits : 21 - 21 (1 bit)
access : read-write

TWEND : TWEND
bits : 22 - 22 (1 bit)
access : read-write

TXRUN : TXRUN
bits : 23 - 23 (1 bit)
access : read-only

ESIOSUE : ESIOSUE
bits : 31 - 31 (1 bit)
access : read-only


PERR

ESIO Parity Error Flag Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERR PERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L0VPERR L1VPERR L2VPERR L3VPERR HPERR VPERR

L0VPERR : L0VPERR
bits : 0 - 1 (2 bit)
access : read-write

L1VPERR : L1VPERR
bits : 2 - 3 (2 bit)
access : read-write

L2VPERR : L2VPERR
bits : 4 - 5 (2 bit)
access : read-write

L3VPERR : L3VPERR
bits : 6 - 7 (2 bit)
access : read-write

HPERR : HPERR
bits : 8 - 8 (1 bit)
access : read-write

VPERR : VPERR
bits : 9 - 9 (1 bit)
access : read-write


HPERR0

ESIO Horizontal Parity Error Register 0
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPERR0 HPERR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L0HP

L0HP : L0HP
bits : 0 - 30 (31 bit)
access : read-write


HPERR1

ESIO Horizontal Parity Error Register 1
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPERR1 HPERR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L1HP

L1HP : L1HP
bits : 0 - 30 (31 bit)
access : read-write


HPERR2

ESIO Horizontal Parity Error Register 2
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPERR2 HPERR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2HP

L2HP : L2HP
bits : 0 - 30 (31 bit)
access : read-write


HPERR3

ESIO Horizontal Parity Error Register 3
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPERR3 HPERR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3HP

L3HP : L3HP
bits : 0 - 30 (31 bit)
access : read-write


VPERR

ESIO Vertical Parity Error Frame Number Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VPERR VPERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L0VPFN L1VPFN L2VPFN L3VPFN

L0VPFN : L0VPFN
bits : 0 - 7 (8 bit)
access : read-write

L1VPFN : L1VPFN
bits : 8 - 15 (8 bit)
access : read-write

L2VPFN : L2VPFN
bits : 16 - 23 (8 bit)
access : read-write

L3VPFN : L3VPFN
bits : 24 - 31 (8 bit)
access : read-write


CR1

ESIO Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC CSSEL TMMD ESIOMS TRXE

FC : FC
bits : 0 - 7 (8 bit)
access : read-write

CSSEL : CSSEL
bits : 8 - 8 (1 bit)
access : read-write

TMMD : TMMD
bits : 10 - 11 (2 bit)
access : read-write

ESIOMS : ESIOMS
bits : 13 - 13 (1 bit)
access : read-write

TRXE : TRXE
bits : 14 - 14 (1 bit)
access : read-write


CR2

ESIO Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARE DMATE INTPERR INTRXWE INTRXFE INTTXWE INTTXFE RIL TIL TXIFV

DMARE : DMARE
bits : 0 - 0 (1 bit)
access : read-write

DMATE : DMATE
bits : 1 - 1 (1 bit)
access : read-write

INTPERR : INTPERR
bits : 2 - 2 (1 bit)
access : read-write

INTRXWE : INTRXWE
bits : 4 - 4 (1 bit)
access : read-write

INTRXFE : INTRXFE
bits : 5 - 5 (1 bit)
access : read-write

INTTXWE : INTTXWE
bits : 6 - 6 (1 bit)
access : read-write

INTTXFE : INTTXFE
bits : 7 - 7 (1 bit)
access : read-write

RIL : RIL
bits : 8 - 11 (4 bit)
access : read-write

TIL : TIL
bits : 12 - 15 (4 bit)
access : read-write

TXIFV : TXIFV
bits : 22 - 23 (2 bit)
access : read-write


CR3

ESIO Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFFLLCLR TFEMPCLR

RFFLLCLR : RFFLLCLR
bits : 0 - 0 (1 bit)
access : write-only

TFEMPCLR : TFEMPCLR
bits : 1 - 1 (1 bit)
access : write-only



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