\n

PU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

OD

PUP

IE

CR

FR1


DATA

Port U Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7

PU0 : PU0
bits : 0 - 0 (1 bit)
access : read-write

PU1 : PU1
bits : 1 - 1 (1 bit)
access : read-write

PU2 : PU2
bits : 2 - 2 (1 bit)
access : read-write

PU3 : PU3
bits : 3 - 3 (1 bit)
access : read-write

PU4 : PU4
bits : 4 - 4 (1 bit)
access : read-write

PU5 : PU5
bits : 5 - 5 (1 bit)
access : read-write

PU6 : PU6
bits : 6 - 6 (1 bit)
access : read-write

PU7 : PU7
bits : 7 - 7 (1 bit)
access : read-write


OD

Port U Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0OD PU1OD PU2OD PU3OD PU4OD PU5OD PU6OD PU7OD

PU0OD : PU0OD
bits : 0 - 0 (1 bit)
access : read-write

PU1OD : PU1OD
bits : 1 - 1 (1 bit)
access : read-write

PU2OD : PU2OD
bits : 2 - 2 (1 bit)
access : read-write

PU3OD : PU3OD
bits : 3 - 3 (1 bit)
access : read-write

PU4OD : PU4OD
bits : 4 - 4 (1 bit)
access : read-write

PU5OD : PU5OD
bits : 5 - 5 (1 bit)
access : read-write

PU6OD : PU6OD
bits : 6 - 6 (1 bit)
access : read-write

PU7OD : PU7OD
bits : 7 - 7 (1 bit)
access : read-write


PUP

Port U Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0UP PU1UP PU2UP PU3UP PU4UP PU5UP PU6UP PU7UP

PU0UP : PU0UP
bits : 0 - 0 (1 bit)
access : read-write

PU1UP : PU1UP
bits : 1 - 1 (1 bit)
access : read-write

PU2UP : PU2UP
bits : 2 - 2 (1 bit)
access : read-write

PU3UP : PU3UP
bits : 3 - 3 (1 bit)
access : read-write

PU4UP : PU4UP
bits : 4 - 4 (1 bit)
access : read-write

PU5UP : PU5UP
bits : 5 - 5 (1 bit)
access : read-write

PU6UP : PU6UP
bits : 6 - 6 (1 bit)
access : read-write

PU7UP : PU7UP
bits : 7 - 7 (1 bit)
access : read-write


IE

Port U Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0IE PU1IE PU2IE PU3IE PU4IE PU5IE PU6IE PU7IE

PU0IE : PU0IE
bits : 0 - 0 (1 bit)
access : read-write

PU1IE : PU1IE
bits : 1 - 1 (1 bit)
access : read-write

PU2IE : PU2IE
bits : 2 - 2 (1 bit)
access : read-write

PU3IE : PU3IE
bits : 3 - 3 (1 bit)
access : read-write

PU4IE : PU4IE
bits : 4 - 4 (1 bit)
access : read-write

PU5IE : PU5IE
bits : 5 - 5 (1 bit)
access : read-write

PU6IE : PU6IE
bits : 6 - 6 (1 bit)
access : read-write

PU7IE : PU7IE
bits : 7 - 7 (1 bit)
access : read-write


CR

Port U Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0C PU1C PU2C PU3C PU4C PU5C PU6C PU7C

PU0C : PU0C
bits : 0 - 0 (1 bit)
access : read-write

PU1C : PU1C
bits : 1 - 1 (1 bit)
access : read-write

PU2C : PU2C
bits : 2 - 2 (1 bit)
access : read-write

PU3C : PU3C
bits : 3 - 3 (1 bit)
access : read-write

PU4C : PU4C
bits : 4 - 4 (1 bit)
access : read-write

PU5C : PU5C
bits : 5 - 5 (1 bit)
access : read-write

PU6C : PU6C
bits : 6 - 6 (1 bit)
access : read-write

PU7C : PU7C
bits : 7 - 7 (1 bit)
access : read-write


FR1

Port U Function Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR1 FR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0F1 PU1F1 PU2F1 PU3F1 PU4F1 PU5F1 PU6F1 PU7F1

PU0F1 : PU0F1
bits : 0 - 0 (1 bit)
access : read-write

PU1F1 : PU1F1
bits : 1 - 1 (1 bit)
access : read-write

PU2F1 : PU2F1
bits : 2 - 2 (1 bit)
access : read-write

PU3F1 : PU3F1
bits : 3 - 3 (1 bit)
access : read-write

PU4F1 : PU4F1
bits : 4 - 4 (1 bit)
access : read-write

PU5F1 : PU5F1
bits : 5 - 5 (1 bit)
access : read-write

PU6F1 : PU6F1
bits : 6 - 6 (1 bit)
access : read-write

PU7F1 : PU7F1
bits : 7 - 7 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.