\n

PV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

OD

PUP

IE

CR

FR1


DATA

Port V Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0 PV1 PV2 PV3 PV4 PV5 PV6 PV7

PV0 : PV0
bits : 0 - 0 (1 bit)
access : read-write

PV1 : PV1
bits : 1 - 1 (1 bit)
access : read-write

PV2 : PV2
bits : 2 - 2 (1 bit)
access : read-write

PV3 : PV3
bits : 3 - 3 (1 bit)
access : read-write

PV4 : PV4
bits : 4 - 4 (1 bit)
access : read-write

PV5 : PV5
bits : 5 - 5 (1 bit)
access : read-write

PV6 : PV6
bits : 6 - 6 (1 bit)
access : read-write

PV7 : PV7
bits : 7 - 7 (1 bit)
access : read-write


OD

Port V Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0OD PV1OD PV2OD PV3OD PV4OD PV5OD PV6OD PV7OD

PV0OD : PV0OD
bits : 0 - 0 (1 bit)
access : read-write

PV1OD : PV1OD
bits : 1 - 1 (1 bit)
access : read-write

PV2OD : PV2OD
bits : 2 - 2 (1 bit)
access : read-write

PV3OD : PV3OD
bits : 3 - 3 (1 bit)
access : read-write

PV4OD : PV4OD
bits : 4 - 4 (1 bit)
access : read-write

PV5OD : PV5OD
bits : 5 - 5 (1 bit)
access : read-write

PV6OD : PV6OD
bits : 6 - 6 (1 bit)
access : read-write

PV7OD : PV7OD
bits : 7 - 7 (1 bit)
access : read-write


PUP

Port V PVll-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0UP PV1UP PV2UP PV3UP PV4UP PV5UP PV6UP PV7UP

PV0UP : PV0UP
bits : 0 - 0 (1 bit)
access : read-write

PV1UP : PV1UP
bits : 1 - 1 (1 bit)
access : read-write

PV2UP : PV2UP
bits : 2 - 2 (1 bit)
access : read-write

PV3UP : PV3UP
bits : 3 - 3 (1 bit)
access : read-write

PV4UP : PV4UP
bits : 4 - 4 (1 bit)
access : read-write

PV5UP : PV5UP
bits : 5 - 5 (1 bit)
access : read-write

PV6UP : PV6UP
bits : 6 - 6 (1 bit)
access : read-write

PV7UP : PV7UP
bits : 7 - 7 (1 bit)
access : read-write


IE

Port V InPVt Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0IE PV1IE PV2IE PV3IE PV4IE PV5IE PV6IE PV7IE

PV0IE : PV0IE
bits : 0 - 0 (1 bit)
access : read-write

PV1IE : PV1IE
bits : 1 - 1 (1 bit)
access : read-write

PV2IE : PV2IE
bits : 2 - 2 (1 bit)
access : read-write

PV3IE : PV3IE
bits : 3 - 3 (1 bit)
access : read-write

PV4IE : PV4IE
bits : 4 - 4 (1 bit)
access : read-write

PV5IE : PV5IE
bits : 5 - 5 (1 bit)
access : read-write

PV6IE : PV6IE
bits : 6 - 6 (1 bit)
access : read-write

PV7IE : PV7IE
bits : 7 - 7 (1 bit)
access : read-write


CR

Port V OutPVt Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0C PV1C PV2C PV3C PV4C PV5C PV6C PV7C

PV0C : PV0C
bits : 0 - 0 (1 bit)
access : read-write

PV1C : PV1C
bits : 1 - 1 (1 bit)
access : read-write

PV2C : PV2C
bits : 2 - 2 (1 bit)
access : read-write

PV3C : PV3C
bits : 3 - 3 (1 bit)
access : read-write

PV4C : PV4C
bits : 4 - 4 (1 bit)
access : read-write

PV5C : PV5C
bits : 5 - 5 (1 bit)
access : read-write

PV6C : PV6C
bits : 6 - 6 (1 bit)
access : read-write

PV7C : PV7C
bits : 7 - 7 (1 bit)
access : read-write


FR1

Port V Function Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR1 FR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0F1 PV1F1 PV2F1 PV3F1 PV4F1 PV5F1 PV6F1 PV7F1

PV0F1 : PV0F1
bits : 0 - 0 (1 bit)
access : read-write

PV1F1 : PV1F1
bits : 1 - 1 (1 bit)
access : read-write

PV2F1 : PV2F1
bits : 2 - 2 (1 bit)
access : read-write

PV3F1 : PV3F1
bits : 3 - 3 (1 bit)
access : read-write

PV4F1 : PV4F1
bits : 4 - 4 (1 bit)
access : read-write

PV5F1 : PV5F1
bits : 5 - 5 (1 bit)
access : read-write

PV6F1 : PV6F1
bits : 6 - 6 (1 bit)
access : read-write

PV7F1 : PV7F1
bits : 7 - 7 (1 bit)
access : read-write



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