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PAG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

OD

PUP

IE

CR

FR1

FR2


DATA

Port AG Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAG0 PAG1 PAG2 PAG3 PAG4 PAG5 PAG6 PAG7

PAG0 : PAG0
bits : 0 - 0 (1 bit)
access : read-write

PAG1 : PAG1
bits : 1 - 1 (1 bit)
access : read-write

PAG2 : PAG2
bits : 2 - 2 (1 bit)
access : read-write

PAG3 : PAG3
bits : 3 - 3 (1 bit)
access : read-write

PAG4 : PAG4
bits : 4 - 4 (1 bit)
access : read-write

PAG5 : PAG5
bits : 5 - 5 (1 bit)
access : read-write

PAG6 : PAG6
bits : 6 - 6 (1 bit)
access : read-write

PAG7 : PAG7
bits : 7 - 7 (1 bit)
access : read-write


OD

Port AG Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAG0OD PAG1OD PAG2OD PAG3OD PAG4OD PAG5OD PAG6OD PAG7OD

PAG0OD : PAG0OD
bits : 0 - 0 (1 bit)
access : read-write

PAG1OD : PAG1OD
bits : 1 - 1 (1 bit)
access : read-write

PAG2OD : PAG2OD
bits : 2 - 2 (1 bit)
access : read-write

PAG3OD : PAG3OD
bits : 3 - 3 (1 bit)
access : read-write

PAG4OD : PAG4OD
bits : 4 - 4 (1 bit)
access : read-write

PAG5OD : PAG5OD
bits : 5 - 5 (1 bit)
access : read-write

PAG6OD : PAG6OD
bits : 6 - 6 (1 bit)
access : read-write

PAG7OD : PAG7OD
bits : 7 - 7 (1 bit)
access : read-write


PUP

Port AG PAGll-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAG0UP PAG1UP PAG2UP PAG3UP PAG4UP PAG5UP PAG6UP PAG7UP

PAG0UP : PAG0UP
bits : 0 - 0 (1 bit)
access : read-write

PAG1UP : PAG1UP
bits : 1 - 1 (1 bit)
access : read-write

PAG2UP : PAG2UP
bits : 2 - 2 (1 bit)
access : read-write

PAG3UP : PAG3UP
bits : 3 - 3 (1 bit)
access : read-write

PAG4UP : PAG4UP
bits : 4 - 4 (1 bit)
access : read-write

PAG5UP : PAG5UP
bits : 5 - 5 (1 bit)
access : read-write

PAG6UP : PAG6UP
bits : 6 - 6 (1 bit)
access : read-write

PAG7UP : PAG7UP
bits : 7 - 7 (1 bit)
access : read-write


IE

Port AG InPAGt Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAG0IE PAG1IE PAG2IE PAG3IE PAG4IE PAG5IE PAG6IE PAG7IE

PAG0IE : PAG0IE
bits : 0 - 0 (1 bit)
access : read-write

PAG1IE : PAG1IE
bits : 1 - 1 (1 bit)
access : read-write

PAG2IE : PAG2IE
bits : 2 - 2 (1 bit)
access : read-write

PAG3IE : PAG3IE
bits : 3 - 3 (1 bit)
access : read-write

PAG4IE : PAG4IE
bits : 4 - 4 (1 bit)
access : read-write

PAG5IE : PAG5IE
bits : 5 - 5 (1 bit)
access : read-write

PAG6IE : PAG6IE
bits : 6 - 6 (1 bit)
access : read-write

PAG7IE : PAG7IE
bits : 7 - 7 (1 bit)
access : read-write


CR

Port AG OutPAGt Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAG0C PAG1C PAG2C PAG3C PAG4C PAG5C PAG6C PAG7C

PAG0C : PAG0C
bits : 0 - 0 (1 bit)
access : read-write

PAG1C : PAG1C
bits : 1 - 1 (1 bit)
access : read-write

PAG2C : PAG2C
bits : 2 - 2 (1 bit)
access : read-write

PAG3C : PAG3C
bits : 3 - 3 (1 bit)
access : read-write

PAG4C : PAG4C
bits : 4 - 4 (1 bit)
access : read-write

PAG5C : PAG5C
bits : 5 - 5 (1 bit)
access : read-write

PAG6C : PAG6C
bits : 6 - 6 (1 bit)
access : read-write

PAG7C : PAG7C
bits : 7 - 7 (1 bit)
access : read-write


FR1

Port AG Function Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR1 FR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAG0F1 PAG1F1 PAG2F1 PAG3F1 PAG4F1 PAG5F1 PAG6F1 PAG7F1

PAG0F1 : PAG0F1
bits : 0 - 0 (1 bit)
access : read-write

PAG1F1 : PAG1F1
bits : 1 - 1 (1 bit)
access : read-write

PAG2F1 : PAG2F1
bits : 2 - 2 (1 bit)
access : read-write

PAG3F1 : PAG3F1
bits : 3 - 3 (1 bit)
access : read-write

PAG4F1 : PAG4F1
bits : 4 - 4 (1 bit)
access : read-write

PAG5F1 : PAG5F1
bits : 5 - 5 (1 bit)
access : read-write

PAG6F1 : PAG6F1
bits : 6 - 6 (1 bit)
access : read-write

PAG7F1 : PAG7F1
bits : 7 - 7 (1 bit)
access : read-write


FR2

Port AG Function Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR2 FR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAG0F2 PAG1F2 PAG2F2 PAG3F2 PAG4F2 PAG5F2 PAG6F2 PAG7F2

PAG0F2 : PAG0F2
bits : 0 - 0 (1 bit)
access : read-write

PAG1F2 : PAG1F2
bits : 1 - 1 (1 bit)
access : read-write

PAG2F2 : PAG2F2
bits : 2 - 2 (1 bit)
access : read-write

PAG3F2 : PAG3F2
bits : 3 - 3 (1 bit)
access : read-write

PAG4F2 : PAG4F2
bits : 4 - 4 (1 bit)
access : read-write

PAG5F2 : PAG5F2
bits : 5 - 5 (1 bit)
access : read-write

PAG6F2 : PAG6F2
bits : 6 - 6 (1 bit)
access : read-write

PAG7F2 : PAG7F2
bits : 7 - 7 (1 bit)
access : read-write



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