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CG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYSCR

CKSEL

PWMGEAR

LKMSKA

LKMSKB

CMSKA

CMSKB

PROTECT

OSCCR

IMCGA

IMCGB

IMCGC

IMCGD

IMCGE

IMCGF

IMCGG

IMCGH

ICRCG

RSTFLG

STBYCR

PLLSEL


SYSCR

System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCR SYSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEAR PRCK FPSEL0 FPSEL1 SCOSEL FCSTOP0 FCSTOP1 FCSTOP2 PSCSTOP

GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write

PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write

FPSEL0 : FPSEL0
bits : 12 - 12 (1 bit)
access : read-write

FPSEL1 : FPSEL1
bits : 13 - 13 (1 bit)
access : read-only

SCOSEL : SCOSEL
bits : 16 - 17 (2 bit)
access : read-write

FCSTOP0 : FCSTOP0
bits : 17 - 17 (1 bit)
access : read-write

FCSTOP1 : FCSTOP1
bits : 18 - 18 (1 bit)
access : read-write

FCSTOP2 : FCSTOP2
bits : 20 - 20 (1 bit)
access : read-write

PSCSTOP : PSCSTOP
bits : 21 - 21 (1 bit)
access : read-write


CKSEL

System Clock Selection Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKSEL CKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCKFLG SYSCK

SYSCKFLG : SYSCKFLG
bits : 0 - 0 (1 bit)
access : read-only

SYSCK : SYSCK
bits : 1 - 1 (1 bit)
access : read-write


PWMGEAR

Timer D Clock Setting Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMGEAR PWMGEAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRDCLKEN TMRDGEAR

TMRDCLKEN : TMRDCLKEN
bits : 0 - 0 (1 bit)
access : read-write

TMRDGEAR : TMRDGEAR
bits : 4 - 5 (2 bit)
access : read-write


LKMSKA

fclk Supply Stop Register A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LKMSKA LKMSKA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRB10 TMRB11 TMRB12 TMRB13 TMRB14 TMRB15 TMRB16 TMRB17 TMRB18 TMRB19 DAC0 DAC1 EBIF UART0 UART1 DMACA DMACB DMACC PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORTH PORTJ PORTK PORTL PORTM PORTN

TMRB10 : TMRB10
bits : 0 - 0 (1 bit)
access : read-write

TMRB11 : TMRB11
bits : 1 - 1 (1 bit)
access : read-write

TMRB12 : TMRB12
bits : 2 - 2 (1 bit)
access : read-write

TMRB13 : TMRB13
bits : 3 - 3 (1 bit)
access : read-write

TMRB14 : TMRB14
bits : 4 - 4 (1 bit)
access : read-write

TMRB15 : TMRB15
bits : 5 - 5 (1 bit)
access : read-write

TMRB16 : TMRB16
bits : 6 - 6 (1 bit)
access : read-write

TMRB17 : TMRB17
bits : 7 - 7 (1 bit)
access : read-write

TMRB18 : TMRB18
bits : 8 - 8 (1 bit)
access : read-write

TMRB19 : TMRB19
bits : 9 - 9 (1 bit)
access : read-write

DAC0 : DAC0
bits : 10 - 10 (1 bit)
access : read-write

DAC1 : DAC1
bits : 11 - 11 (1 bit)
access : read-write

EBIF : EBIF
bits : 12 - 12 (1 bit)
access : read-write

UART0 : UART0
bits : 13 - 13 (1 bit)
access : read-write

UART1 : UART1
bits : 14 - 14 (1 bit)
access : read-write

DMACA : DMACA
bits : 15 - 15 (1 bit)
access : read-write

DMACB : DMACB
bits : 16 - 16 (1 bit)
access : read-write

DMACC : DMACC
bits : 17 - 17 (1 bit)
access : read-write

PORTA : PORTA
bits : 19 - 19 (1 bit)
access : read-write

PORTB : PORTB
bits : 20 - 20 (1 bit)
access : read-write

PORTC : PORTC
bits : 21 - 21 (1 bit)
access : read-write

PORTD : PORTD
bits : 22 - 22 (1 bit)
access : read-write

PORTE : PORTE
bits : 23 - 23 (1 bit)
access : read-write

PORTF : PORTF
bits : 24 - 24 (1 bit)
access : read-write

PORTG : PORTG
bits : 25 - 25 (1 bit)
access : read-write

PORTH : PORTH
bits : 26 - 26 (1 bit)
access : read-write

PORTJ : PORTJ
bits : 27 - 27 (1 bit)
access : read-write

PORTK : PORTK
bits : 28 - 28 (1 bit)
access : read-write

PORTL : PORTL
bits : 29 - 29 (1 bit)
access : read-write

PORTM : PORTM
bits : 30 - 30 (1 bit)
access : read-write

PORTN : PORTN
bits : 31 - 31 (1 bit)
access : read-write


LKMSKB

fclk Supply Stop Register B
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LKMSKB LKMSKB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTP PORTR PORTT PORTU PORTV PORTW PORTY PORTAA PORTAB PORTAC PORTAD PORTAE PORTAF PORTAG PORTAH PORTAJ ADCA ADCB ADCC EPHC SBI WDT

PORTP : PORTP
bits : 0 - 0 (1 bit)
access : read-write

PORTR : PORTR
bits : 1 - 1 (1 bit)
access : read-write

PORTT : PORTT
bits : 2 - 2 (1 bit)
access : read-write

PORTU : PORTU
bits : 3 - 3 (1 bit)
access : read-write

PORTV : PORTV
bits : 4 - 4 (1 bit)
access : read-write

PORTW : PORTW
bits : 5 - 5 (1 bit)
access : read-write

PORTY : PORTY
bits : 6 - 6 (1 bit)
access : read-write

PORTAA : PORTAA
bits : 7 - 7 (1 bit)
access : read-write

PORTAB : PORTAB
bits : 8 - 8 (1 bit)
access : read-write

PORTAC : PORTAC
bits : 9 - 9 (1 bit)
access : read-write

PORTAD : PORTAD
bits : 10 - 10 (1 bit)
access : read-write

PORTAE : PORTAE
bits : 11 - 11 (1 bit)
access : read-write

PORTAF : PORTAF
bits : 12 - 12 (1 bit)
access : read-write

PORTAG : PORTAG
bits : 13 - 13 (1 bit)
access : read-write

PORTAH : PORTAH
bits : 14 - 14 (1 bit)
access : read-write

PORTAJ : PORTAJ
bits : 15 - 15 (1 bit)
access : read-write

ADCA : ADCA
bits : 17 - 17 (1 bit)
access : read-write

ADCB : ADCB
bits : 18 - 18 (1 bit)
access : read-write

ADCC : ADCC
bits : 19 - 19 (1 bit)
access : read-write

EPHC : EPHC
bits : 20 - 20 (1 bit)
access : read-write

SBI : SBI
bits : 21 - 21 (1 bit)
access : read-write

WDT : WDT
bits : 22 - 22 (1 bit)
access : read-write


CMSKA

fc Supply Stop Register A
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMSKA CMSKA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESIO0 ESIO1 ESIO2 TMRD SIO_UART0 SIO_UART1 SIO_UART2 SIO_UART3 SIO_UART4 SIO_UART5 TMRB00 TMRB01 TMRB02 TMRB03 TMRB04 TMRB05 TMRB06 TMRB07 TMRB08 TMRB09 TMRCCAP0 TMRCCAP1 TMRCCAP2 TMRCCAP3 TMRCCMP0 TMRCCMP1 TMRCCMP2 TMRCCMP3 TMRCCMP4 TMRCCMP5 TMRCCMP6 TMRCCMP7

ESIO0 : ESIO0
bits : 0 - 0 (1 bit)
access : read-write

ESIO1 : ESIO1
bits : 1 - 1 (1 bit)
access : read-write

ESIO2 : ESIO2
bits : 2 - 2 (1 bit)
access : read-write

TMRD : TMRD
bits : 3 - 3 (1 bit)
access : read-write

SIO_UART0 : SIO_UART0
bits : 4 - 4 (1 bit)
access : read-write

SIO_UART1 : SIO_UART1
bits : 5 - 5 (1 bit)
access : read-write

SIO_UART2 : SIO_UART2
bits : 6 - 6 (1 bit)
access : read-write

SIO_UART3 : SIO_UART3
bits : 7 - 7 (1 bit)
access : read-write

SIO_UART4 : SIO_UART4
bits : 8 - 8 (1 bit)
access : read-write

SIO_UART5 : SIO_UART5
bits : 9 - 9 (1 bit)
access : read-write

TMRB00 : TMRB00
bits : 10 - 10 (1 bit)
access : read-write

TMRB01 : TMRB01
bits : 11 - 11 (1 bit)
access : read-write

TMRB02 : TMRB02
bits : 12 - 12 (1 bit)
access : read-write

TMRB03 : TMRB03
bits : 13 - 13 (1 bit)
access : read-write

TMRB04 : TMRB04
bits : 14 - 14 (1 bit)
access : read-write

TMRB05 : TMRB05
bits : 15 - 15 (1 bit)
access : read-write

TMRB06 : TMRB06
bits : 16 - 16 (1 bit)
access : read-write

TMRB07 : TMRB07
bits : 17 - 17 (1 bit)
access : read-write

TMRB08 : TMRB08
bits : 18 - 18 (1 bit)
access : read-write

TMRB09 : TMRB09
bits : 19 - 19 (1 bit)
access : read-write

TMRCCAP0 : TMRCCAP0
bits : 20 - 20 (1 bit)
access : read-write

TMRCCAP1 : TMRCCAP1
bits : 21 - 21 (1 bit)
access : read-write

TMRCCAP2 : TMRCCAP2
bits : 22 - 22 (1 bit)
access : read-write

TMRCCAP3 : TMRCCAP3
bits : 23 - 23 (1 bit)
access : read-write

TMRCCMP0 : TMRCCMP0
bits : 24 - 24 (1 bit)
access : read-write

TMRCCMP1 : TMRCCMP1
bits : 25 - 25 (1 bit)
access : read-write

TMRCCMP2 : TMRCCMP2
bits : 26 - 26 (1 bit)
access : read-write

TMRCCMP3 : TMRCCMP3
bits : 27 - 27 (1 bit)
access : read-write

TMRCCMP4 : TMRCCMP4
bits : 28 - 28 (1 bit)
access : read-write

TMRCCMP5 : TMRCCMP5
bits : 29 - 29 (1 bit)
access : read-write

TMRCCMP6 : TMRCCMP6
bits : 30 - 30 (1 bit)
access : read-write

TMRCCMP7 : TMRCCMP7
bits : 31 - 31 (1 bit)
access : read-write


CMSKB

fc Supply Stop Register B
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMSKB CMSKB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRCTBT

TMRCTBT : TMRCTBT
bits : 0 - 0 (1 bit)
access : read-write


PROTECT

Protect Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTECT PROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGPROTECT

CGPROTECT : CGPROTECT
bits : 0 - 7 (8 bit)
access : read-write


OSCCR

Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCR OSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUEON WUEF PLL0ON WUPSEL1 WUPT XEN1 XTEN PLL1ON WUPTL XEN2 OSCSEL EHOSCSEL WUPSEL2 WUPT

WUEON : WUEON
bits : 0 - 0 (1 bit)
access : write-only

WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only

PLL0ON : PLL0ON
bits : 2 - 2 (1 bit)
access : read-write

WUPSEL1 : WUPSEL1
bits : 3 - 3 (1 bit)
access : read-write

WUPT : WUPT
bits : 4 - 7 (4 bit)
access : read-only

XEN1 : XEN1
bits : 8 - 8 (1 bit)
access : read-write

XTEN : XTEN
bits : 9 - 9 (1 bit)
access : read-write

PLL1ON : PLL1ON
bits : 10 - 10 (1 bit)
access : read-write

WUPTL : WUPTL
bits : 14 - 15 (2 bit)
access : read-write

XEN2 : XEN2
bits : 16 - 16 (1 bit)
access : read-write

OSCSEL : OSCSEL
bits : 17 - 17 (1 bit)
access : read-write

EHOSCSEL : EHOSCSEL
bits : 18 - 18 (1 bit)
access : read-write

WUPSEL2 : WUPSEL2
bits : 19 - 19 (1 bit)
access : read-write

WUPT : WUPT
bits : 20 - 31 (12 bit)
access : read-write


IMCGA

CG Interrupt Mode Control Register A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGA IMCGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT00EN EMST00 EMCG00 INT01EN EMST01 EMCG01 INT02EN EMST02 EMCG02 INT03EN EMST03 EMCG03

INT00EN : INT00EN
bits : 0 - 0 (1 bit)
access : read-write

EMST00 : EMST00
bits : 2 - 3 (2 bit)
access : read-only

EMCG00 : EMCG00
bits : 4 - 6 (3 bit)
access : read-write

INT01EN : INT01EN
bits : 8 - 8 (1 bit)
access : read-write

EMST01 : EMST01
bits : 10 - 11 (2 bit)
access : read-only

EMCG01 : EMCG01
bits : 12 - 14 (3 bit)
access : read-write

INT02EN : INT02EN
bits : 16 - 16 (1 bit)
access : read-write

EMST02 : EMST02
bits : 18 - 19 (2 bit)
access : read-only

EMCG02 : EMCG02
bits : 20 - 22 (3 bit)
access : read-write

INT03EN : INT03EN
bits : 24 - 24 (1 bit)
access : read-write

EMST03 : EMST03
bits : 26 - 27 (2 bit)
access : read-only

EMCG03 : EMCG03
bits : 28 - 30 (3 bit)
access : read-write


IMCGB

CG Interrupt Mode Control Register B
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGB IMCGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT04EN EMST04 EMCG04 INT05EN EMST05 EMCG05 INT6EN EMST06 EMCG06 INT07EN EMST07 EMCG07

INT04EN : INT04EN
bits : 0 - 0 (1 bit)
access : read-write

EMST04 : EMST04
bits : 2 - 3 (2 bit)
access : read-only

EMCG04 : EMCG04
bits : 4 - 6 (3 bit)
access : read-write

INT05EN : INT05EN
bits : 8 - 8 (1 bit)
access : read-write

EMST05 : EMST05
bits : 10 - 11 (2 bit)
access : read-only

EMCG05 : EMCG05
bits : 12 - 14 (3 bit)
access : read-write

INT6EN : INT6EN
bits : 16 - 16 (1 bit)
access : read-write

EMST06 : EMST06
bits : 18 - 19 (2 bit)
access : read-only

EMCG06 : EMCG06
bits : 20 - 22 (3 bit)
access : read-write

INT07EN : INT07EN
bits : 24 - 24 (1 bit)
access : read-write

EMST07 : EMST07
bits : 26 - 27 (2 bit)
access : read-only

EMCG07 : EMCG07
bits : 28 - 30 (3 bit)
access : read-write


IMCGC

CG Interrupt Mode Control Register C
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGC IMCGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT08EN EMST08 EMCG08 INT09EN EMST09 EMCG09 INT0AEN EMST0A EMCG0A INT0BEN EMST0B EMCG0B

INT08EN : INT08EN
bits : 0 - 0 (1 bit)
access : read-write

EMST08 : EMST08
bits : 2 - 3 (2 bit)
access : read-only

EMCG08 : EMCG08
bits : 4 - 6 (3 bit)
access : read-write

INT09EN : INT09EN
bits : 8 - 8 (1 bit)
access : read-write

EMST09 : EMST09
bits : 10 - 11 (2 bit)
access : read-only

EMCG09 : EMCG09
bits : 12 - 14 (3 bit)
access : read-write

INT0AEN : INT0AEN
bits : 16 - 16 (1 bit)
access : read-write

EMST0A : EMST0A
bits : 18 - 19 (2 bit)
access : read-only

EMCG0A : EMCG0A
bits : 20 - 22 (3 bit)
access : read-write

INT0BEN : INT0BEN
bits : 24 - 24 (1 bit)
access : read-write

EMST0B : EMST0B
bits : 26 - 27 (2 bit)
access : read-only

EMCG0B : EMCG0B
bits : 28 - 30 (3 bit)
access : read-write


IMCGD

CG Interrupt Mode Control Register D
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGD IMCGD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT0CEN EMST0C EMCG0C INT0DEN EMST0D EMCG0D INT0EEN EMST0E EMCG0E INT0FEN EMST0F EMCG0F

INT0CEN : INT0CEN
bits : 0 - 0 (1 bit)
access : read-write

EMST0C : EMST0C
bits : 2 - 3 (2 bit)
access : read-only

EMCG0C : EMCG0C
bits : 4 - 6 (3 bit)
access : read-write

INT0DEN : INT0DEN
bits : 8 - 8 (1 bit)
access : read-write

EMST0D : EMST0D
bits : 10 - 11 (2 bit)
access : read-only

EMCG0D : EMCG0D
bits : 12 - 14 (3 bit)
access : read-write

INT0EEN : INT0EEN
bits : 16 - 16 (1 bit)
access : read-write

EMST0E : EMST0E
bits : 18 - 19 (2 bit)
access : read-only

EMCG0E : EMCG0E
bits : 20 - 22 (3 bit)
access : read-write

INT0FEN : INT0FEN
bits : 24 - 24 (1 bit)
access : read-write

EMST0F : EMST0F
bits : 26 - 27 (2 bit)
access : read-only

EMCG0F : EMCG0F
bits : 28 - 30 (3 bit)
access : read-write


IMCGE

CG Interrupt Mode Control Register E
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGE IMCGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT10EN EMST10 EMCG10 INT11EN EMST11 EMCG11 INT12EN EMST12 EMCG12 INT13EN EMST13 EMCG13

INT10EN : INT10EN
bits : 0 - 0 (1 bit)
access : read-write

EMST10 : EMST10
bits : 2 - 3 (2 bit)
access : read-only

EMCG10 : EMCG10
bits : 4 - 6 (3 bit)
access : read-write

INT11EN : INT11EN
bits : 8 - 8 (1 bit)
access : read-write

EMST11 : EMST11
bits : 10 - 11 (2 bit)
access : read-only

EMCG11 : EMCG11
bits : 12 - 14 (3 bit)
access : read-write

INT12EN : INT12EN
bits : 16 - 16 (1 bit)
access : read-write

EMST12 : EMST12
bits : 18 - 19 (2 bit)
access : read-only

EMCG12 : EMCG12
bits : 20 - 22 (3 bit)
access : read-write

INT13EN : INT13EN
bits : 24 - 24 (1 bit)
access : read-write

EMST13 : EMST13
bits : 26 - 27 (2 bit)
access : read-only

EMCG13 : EMCG13
bits : 28 - 30 (3 bit)
access : read-write


IMCGF

CG Interrupt Mode Control Register F
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGF IMCGF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT14EN EMST14 EMCG14 INT15EN EMST15 EMCG15 INT16EN EMST16 EMCG16 INT17EN EMST17 EMCG17

INT14EN : INT14EN
bits : 0 - 0 (1 bit)
access : read-write

EMST14 : EMST14
bits : 2 - 3 (2 bit)
access : read-only

EMCG14 : EMCG14
bits : 4 - 6 (3 bit)
access : read-write

INT15EN : INT15EN
bits : 8 - 8 (1 bit)
access : read-write

EMST15 : EMST15
bits : 10 - 11 (2 bit)
access : read-only

EMCG15 : EMCG15
bits : 12 - 14 (3 bit)
access : read-write

INT16EN : INT16EN
bits : 16 - 16 (1 bit)
access : read-write

EMST16 : EMST16
bits : 18 - 19 (2 bit)
access : read-only

EMCG16 : EMCG16
bits : 20 - 22 (3 bit)
access : read-write

INT17EN : INT17EN
bits : 24 - 24 (1 bit)
access : read-write

EMST17 : EMST17
bits : 26 - 27 (2 bit)
access : read-only

EMCG17 : EMCG17
bits : 28 - 30 (3 bit)
access : read-write


IMCGG

CG Interrupt Mode Control Register G
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGG IMCGG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT18EN EMST18 EMCG18 INT19EN EMST19 EMCG19 INT1AEN EMST1A EMCG1A INT1BEN EMST1B EMCG1B

INT18EN : INT18EN
bits : 0 - 0 (1 bit)
access : read-write

EMST18 : EMST18
bits : 2 - 3 (2 bit)
access : read-only

EMCG18 : EMCG18
bits : 4 - 6 (3 bit)
access : read-write

INT19EN : INT19EN
bits : 8 - 8 (1 bit)
access : read-write

EMST19 : EMST19
bits : 10 - 11 (2 bit)
access : read-only

EMCG19 : EMCG19
bits : 12 - 14 (3 bit)
access : read-write

INT1AEN : INT1AEN
bits : 16 - 16 (1 bit)
access : read-write

EMST1A : EMST1A
bits : 18 - 19 (2 bit)
access : read-only

EMCG1A : EMCG1A
bits : 20 - 22 (3 bit)
access : read-write

INT1BEN : INT1BEN
bits : 24 - 24 (1 bit)
access : read-write

EMST1B : EMST1B
bits : 26 - 27 (2 bit)
access : read-only

EMCG1B : EMCG1B
bits : 28 - 30 (3 bit)
access : read-write


IMCGH

CG Interrupt Mode Control Register H
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGH IMCGH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT1CEN EMST1C EMCG1C INT1DEN EMST1D EMCG1D INT1EEN EMST1E EMCG1E INT1FEN EMST1F EMCG1F

INT1CEN : INT1CEN
bits : 0 - 0 (1 bit)
access : read-write

EMST1C : EMST1C
bits : 2 - 3 (2 bit)
access : read-only

EMCG1C : EMCG1C
bits : 4 - 6 (3 bit)
access : read-write

INT1DEN : INT1DEN
bits : 8 - 8 (1 bit)
access : read-write

EMST1D : EMST1D
bits : 10 - 11 (2 bit)
access : read-only

EMCG1D : EMCG1D
bits : 12 - 14 (3 bit)
access : read-write

INT1EEN : INT1EEN
bits : 16 - 16 (1 bit)
access : read-write

EMST1E : EMST1E
bits : 18 - 19 (2 bit)
access : read-only

EMCG1E : EMCG1E
bits : 20 - 22 (3 bit)
access : read-write

INT1FEN : INT1FEN
bits : 24 - 24 (1 bit)
access : read-write

EMST1F : EMST1F
bits : 26 - 27 (2 bit)
access : read-only

EMCG1F : EMCG1F
bits : 28 - 30 (3 bit)
access : read-write


ICRCG

CG Interrupt Request Clear Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICRCG ICRCG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICRCG

ICRCG : ICRCG
bits : 0 - 4 (5 bit)
access : write-only


RSTFLG

Reset Flag Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTFLG RSTFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PONRSTF0 PINRSTF WDTRSTF BUPRSTF SYSRSTF PONRSTF1

PONRSTF0 : PONRSTF0
bits : 0 - 0 (1 bit)
access : read-write

PINRSTF : PINRSTF
bits : 1 - 1 (1 bit)
access : read-write

WDTRSTF : WDTRSTF
bits : 2 - 2 (1 bit)
access : read-write

BUPRSTF : BUPRSTF
bits : 3 - 3 (1 bit)
access : read-write

SYSRSTF : SYSRSTF
bits : 4 - 4 (1 bit)
access : read-write

PONRSTF1 : PONRSTF1
bits : 6 - 6 (1 bit)
access : read-only


STBYCR

Standby Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STBYCR STBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY DRVE PTKEEP

STBY : STBY
bits : 0 - 2 (3 bit)
access : read-write

DRVE : DRVE
bits : 16 - 16 (1 bit)
access : read-write

PTKEEP : PTKEEP
bits : 17 - 17 (1 bit)
access : read-write


PLLSEL

PLL Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSEL PLLSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL0SEL PLL0SET PLL1SEL PLL1SETL PLL1SETH

PLL0SEL : PLL0SEL
bits : 0 - 0 (1 bit)
access : read-write

PLL0SET : PLL0SET
bits : 1 - 15 (15 bit)
access : read-write

PLL1SEL : PLL1SEL
bits : 16 - 16 (1 bit)
access : read-write

PLL1SETL : PLL1SETL
bits : 17 - 26 (10 bit)
access : read-write

PLL1SETH : PLL1SETH
bits : 28 - 31 (4 bit)
access : read-write



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