\n

KS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EN

CTR

BR0

BR1

BMR0

BMR1

INTCR

ICR

OCR

CR


EN

Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN SC

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

SC : SC
bits : 1 - 1 (1 bit)
access : read-write


CTR

Count Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTR CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCT STP

RCT : RCT
bits : 0 - 7 (8 bit)
access : read-write

STP : STP
bits : 8 - 10 (3 bit)
access : read-write


BR0

Buffer0 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BR0 BR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 B1 B2 B3

B0 : B0
bits : 0 - 7 (8 bit)
access : read-only

B1 : B1
bits : 8 - 15 (8 bit)
access : read-only

B2 : B2
bits : 16 - 23 (8 bit)
access : read-only

B3 : B3
bits : 24 - 31 (8 bit)
access : read-only


BR1

Buffer1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BR1 BR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 B5 B6 B7

B4 : B4
bits : 0 - 7 (8 bit)
access : read-only

B5 : B5
bits : 8 - 15 (8 bit)
access : read-only

B6 : B6
bits : 16 - 23 (8 bit)
access : read-only

B7 : B7
bits : 24 - 31 (8 bit)
access : read-only


BMR0

Buffer0 Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMR0 BMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BM0 BM1 BM2 BM3

BM0 : BM0
bits : 0 - 7 (8 bit)
access : read-write

BM1 : BM1
bits : 8 - 15 (8 bit)
access : read-write

BM2 : BM2
bits : 16 - 23 (8 bit)
access : read-write

BM3 : BM3
bits : 24 - 31 (8 bit)
access : read-write


BMR1

Buffer1 Mask Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMR1 BMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BM4 BM5 BM6 BM7

BM4 : BM4
bits : 0 - 7 (8 bit)
access : read-write

BM5 : BM5
bits : 8 - 15 (8 bit)
access : read-write

BM6 : BM6
bits : 16 - 23 (8 bit)
access : read-write

BM7 : BM7
bits : 24 - 31 (8 bit)
access : read-write


INTCR

Interrupt Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCR INTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTEN

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write


ICR

Key Input Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

KSI0 : KSI0
bits : 0 - 0 (1 bit)
access : read-write

KSI1 : KSI1
bits : 1 - 1 (1 bit)
access : read-write

KSI2 : KSI2
bits : 2 - 2 (1 bit)
access : read-write

KSI3 : KSI3
bits : 3 - 3 (1 bit)
access : read-write

KSI4 : KSI4
bits : 4 - 4 (1 bit)
access : read-write

KSI5 : KSI5
bits : 5 - 5 (1 bit)
access : read-write

KSI6 : KSI6
bits : 6 - 6 (1 bit)
access : read-write

KSI7 : KSI7
bits : 7 - 7 (1 bit)
access : read-write


OCR

Key Output Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCR OCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSLO0 KSLO1 KSLO2 KSLO3 KSLO4 KSLO5 KSLO6 KSLO7

KSO0 : KSO0
bits : 0 - 0 (1 bit)
access : read-write

KSO1 : KSO1
bits : 1 - 1 (1 bit)
access : read-write

KSO2 : KSO2
bits : 2 - 2 (1 bit)
access : read-write

KSO3 : KSO3
bits : 3 - 3 (1 bit)
access : read-write

KSO4 : KSO4
bits : 4 - 4 (1 bit)
access : read-write

KSO5 : KSO5
bits : 5 - 5 (1 bit)
access : read-write

KSO6 : KSO6
bits : 6 - 6 (1 bit)
access : read-write

KSO7 : KSO7
bits : 7 - 7 (1 bit)
access : read-write

KSLO0 : KSLO0
bits : 8 - 8 (1 bit)
access : read-write

KSLO1 : KSLO1
bits : 9 - 9 (1 bit)
access : read-write

KSLO2 : KSLO2
bits : 10 - 10 (1 bit)
access : read-write

KSLO3 : KSLO3
bits : 11 - 11 (1 bit)
access : read-write

KSLO4 : KSLO4
bits : 12 - 12 (1 bit)
access : read-write

KSLO5 : KSLO5
bits : 13 - 13 (1 bit)
access : read-write

KSLO6 : KSLO6
bits : 14 - 14 (1 bit)
access : read-write

KSLO7 : KSLO7
bits : 15 - 15 (1 bit)
access : read-write


CR

Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START BRRST SWRST CMPCNT

START : START
bits : 0 - 0 (1 bit)
access : read-write

BRRST : BRRST
bits : 1 - 1 (1 bit)
access : write-only

SWRST : SWRST
bits : 2 - 3 (2 bit)
access : read-write

CMPCNT : CMPCNT
bits : 4 - 4 (1 bit)
access : read-write



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