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UART0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DR

FR

ILPR

IBRD

FBRD

LCR_H

CR

IFLS

IMSC

RIS

RSR

ECR

MIS

ICR

DMACR


DR

Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA FE PE BE OE

DATA : DATA
bits : 0 - 7 (8 bit)
access : read-write

FE : FE
bits : 8 - 8 (1 bit)
access : read-only

PE : PE
bits : 9 - 9 (1 bit)
access : read-only

BE : BE
bits : 10 - 10 (1 bit)
access : read-only

OE : OE
bits : 11 - 11 (1 bit)
access : read-only


FR

Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FR FR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTS DSR DCD BUSY RXFE TXFF RXFF TXFE RI

CTS : CTS
bits : 0 - 0 (1 bit)
access : read-only

DSR : DSR
bits : 1 - 1 (1 bit)
access : read-only

DCD : DCD
bits : 2 - 2 (1 bit)
access : read-only

BUSY : BUSY
bits : 3 - 3 (1 bit)
access : read-only

RXFE : RXFE
bits : 4 - 4 (1 bit)
access : read-only

TXFF : TXFF
bits : 5 - 5 (1 bit)
access : read-only

RXFF : RXFF
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

RI : RI
bits : 8 - 8 (1 bit)
access : read-only


ILPR

UART IrDA lowPower count register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ILPR ILPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ILPDVSR

ILPDVSR : ILPDVSR
bits : 0 - 7 (8 bit)
access : read-write


IBRD

Integer Baud Rate Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IBRD IBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAUDDIVINT

BAUDDIVINT : BAUDDIVINT
bits : 0 - 15 (16 bit)
access : read-write


FBRD

Fractional Baud Rate Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FBRD FBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAUDDIVFRAC

BAUDDIVFRAC : BAUDDIVFRAC
bits : 0 - 5 (6 bit)
access : read-write


LCR_H

Line Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR_H LCR_H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRK PEN EPS STP2 FEN WLEN SPS

BRK : BRK
bits : 0 - 0 (1 bit)
access : read-write

PEN : PEN
bits : 1 - 1 (1 bit)
access : read-write

EPS : EPS
bits : 2 - 2 (1 bit)
access : read-write

STP2 : STP2
bits : 3 - 3 (1 bit)
access : read-write

FEN : FEN
bits : 4 - 4 (1 bit)
access : read-write

WLEN : WLEN
bits : 5 - 6 (2 bit)
access : read-write

SPS : SPS
bits : 7 - 7 (1 bit)
access : read-write


CR

Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UARTEN SIREN SIRLP TXE RXE DTR RTS RTSEN CTSEN

UARTEN : UARTEN
bits : 0 - 0 (1 bit)
access : read-write

SIREN : SIREN
bits : 1 - 1 (1 bit)
access : read-write

SIRLP : SIRLP
bits : 2 - 2 (1 bit)
access : read-write

TXE : TXE
bits : 8 - 8 (1 bit)
access : read-write

RXE : RXE
bits : 9 - 9 (1 bit)
access : read-write

DTR : DTR
bits : 10 - 10 (1 bit)
access : read-write

RTS : RTS
bits : 11 - 11 (1 bit)
access : read-write

RTSEN : RTSEN
bits : 14 - 14 (1 bit)
access : read-write

CTSEN : CTSEN
bits : 15 - 15 (1 bit)
access : read-write


IFLS

Interrupt FIFO Level Select Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFLS IFLS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXIFLSEL RXIFLSEL

TXIFLSEL : TXIFLSEL
bits : 0 - 2 (3 bit)
access : read-write

RXIFLSEL : RXIFLSEL
bits : 3 - 5 (3 bit)
access : read-write


IMSC

Interrupt Mask Set_Clear Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMSC IMSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIMIM CTSMIM DCDMIM DSRMIM RXIM TXIM RTIM FEIM PEIM BEIM OEIM

RIMIM : RIMIM
bits : 0 - 0 (1 bit)
access : read-write

CTSMIM : CTSMIM
bits : 1 - 1 (1 bit)
access : read-write

DCDMIM : DCDMIM
bits : 2 - 2 (1 bit)
access : read-write

DSRMIM : DSRMIM
bits : 3 - 3 (1 bit)
access : read-write

RXIM : RXIM
bits : 4 - 4 (1 bit)
access : read-write

TXIM : TXIM
bits : 5 - 5 (1 bit)
access : read-write

RTIM : RTIM
bits : 6 - 6 (1 bit)
access : read-write

FEIM : FEIM
bits : 7 - 7 (1 bit)
access : read-write

PEIM : PEIM
bits : 8 - 8 (1 bit)
access : read-write

BEIM : BEIM
bits : 9 - 9 (1 bit)
access : read-write

OEIM : OEIM
bits : 10 - 10 (1 bit)
access : read-write


RIS

Raw Interrupt Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIRMIS CTSRMIS DCDRMIS DSRRMIS RXRIS TXRIS RTRIS FERIS PERIS BERIS OERIS

RIRMIS : RIRMIS
bits : 0 - 0 (1 bit)
access : read-only

CTSRMIS : CTSRMIS
bits : 1 - 1 (1 bit)
access : read-only

DCDRMIS : DCDRMIS
bits : 2 - 2 (1 bit)
access : read-only

DSRRMIS : DSRRMIS
bits : 3 - 3 (1 bit)
access : read-only

RXRIS : RXRIS
bits : 4 - 4 (1 bit)
access : read-only

TXRIS : TXRIS
bits : 5 - 5 (1 bit)
access : read-only

RTRIS : RTRIS
bits : 6 - 6 (1 bit)
access : read-only

FERIS : FERIS
bits : 7 - 7 (1 bit)
access : read-only

PERIS : PERIS
bits : 8 - 8 (1 bit)
access : read-only

BERIS : BERIS
bits : 9 - 9 (1 bit)
access : read-only

OERIS : OERIS
bits : 10 - 10 (1 bit)
access : read-only


RSR

Receive Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSR RSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE PE BE OE

FE : FE
bits : 0 - 0 (1 bit)
access : read-only

PE : PE
bits : 1 - 1 (1 bit)
access : read-only

BE : BE
bits : 2 - 2 (1 bit)
access : read-only

OE : OE
bits : 3 - 3 (1 bit)
access : read-only


ECR

Error Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ECR ECR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE PE BE OE

FE : FE
bits : 0 - 0 (1 bit)
access : write-only

PE : PE
bits : 1 - 1 (1 bit)
access : write-only

BE : BE
bits : 2 - 2 (1 bit)
access : write-only

OE : OE
bits : 3 - 3 (1 bit)
access : write-only


MIS

Masked Interrupt Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIMMIS CTSMMIS DCDMMIS DSRMMIS RXMIS TXMIS RTMIS FEMIS PEMIS BEMIS OEMIS

RIMMIS : RIMMIS
bits : 0 - 0 (1 bit)
access : read-only

CTSMMIS : CTSMMIS
bits : 1 - 1 (1 bit)
access : read-only

DCDMMIS : DCDMMIS
bits : 2 - 2 (1 bit)
access : read-only

DSRMMIS : DSRMMIS
bits : 3 - 3 (1 bit)
access : read-only

RXMIS : RXMIS
bits : 4 - 4 (1 bit)
access : read-only

TXMIS : TXMIS
bits : 5 - 5 (1 bit)
access : read-only

RTMIS : RTMIS
bits : 6 - 6 (1 bit)
access : read-only

FEMIS : FEMIS
bits : 7 - 7 (1 bit)
access : read-only

PEMIS : PEMIS
bits : 8 - 8 (1 bit)
access : read-only

BEMIS : BEMIS
bits : 9 - 9 (1 bit)
access : read-only

OEMIS : OEMIS
bits : 10 - 10 (1 bit)
access : read-only


ICR

Interrupt Clear Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIMIC CTSMIC DCDMIC DSRMIC RXIC TXIC RTIC FEIC PEIC BEIC OEIC

RIMIC : RIMIC
bits : 0 - 0 (1 bit)
access : write-only

CTSMIC : CTSMIC
bits : 1 - 1 (1 bit)
access : write-only

DCDMIC : DCDMIC
bits : 2 - 2 (1 bit)
access : write-only

DSRMIC : DSRMIC
bits : 3 - 3 (1 bit)
access : write-only

RXIC : RXIC
bits : 4 - 4 (1 bit)
access : write-only

TXIC : TXIC
bits : 5 - 5 (1 bit)
access : write-only

RTIC : RTIC
bits : 6 - 6 (1 bit)
access : write-only

FEIC : FEIC
bits : 7 - 7 (1 bit)
access : write-only

PEIC : PEIC
bits : 8 - 8 (1 bit)
access : write-only

BEIC : BEIC
bits : 9 - 9 (1 bit)
access : write-only

OEIC : OEIC
bits : 10 - 10 (1 bit)
access : write-only


DMACR

DMA Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACR DMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAE TXDMAE DMAONERR

RXDMAE : RXDMAE
bits : 0 - 0 (1 bit)
access : read-write

TXDMAE : TXDMAE
bits : 1 - 1 (1 bit)
access : read-write

DMAONERR : DMAONERR
bits : 2 - 2 (1 bit)
access : read-write



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