\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected
External Bus Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXBSEL : EXBSEL
bits : 0 - 0 (1 bit)
access : read-write
EXBWAIT : EXBWAIT
bits : 1 - 2 (2 bit)
access : read-write
External Bus Base Address and CS Space setting Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXAR : EXAR
bits : 0 - 7 (8 bit)
access : read-write
SA : SA
bits : 16 - 31 (16 bit)
access : read-write
External Bus Base Address and CS Space setting Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXAR : EXAR
bits : 0 - 7 (8 bit)
access : read-write
SA : SA
bits : 16 - 31 (16 bit)
access : read-write
External Bus Base Address and CS Space setting Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXAR : EXAR
bits : 0 - 7 (8 bit)
access : read-write
SA : SA
bits : 16 - 31 (16 bit)
access : read-write
External Bus Base Address and CS Space setting Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXAR : EXAR
bits : 0 - 7 (8 bit)
access : read-write
SA : SA
bits : 16 - 31 (16 bit)
access : read-write
Chip Select and Wait Controller Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSW0 : CSW0
bits : 0 - 0 (1 bit)
access : read-write
CSW : CSW
bits : 1 - 2 (2 bit)
access : read-write
CSIW : CSIW
bits : 8 - 11 (4 bit)
access : read-write
WAIT : WAIT
bits : 12 - 12 (1 bit)
access : read-write
WSEL : WSEL
bits : 13 - 13 (1 bit)
access : read-write
RDS : RDS
bits : 16 - 17 (2 bit)
access : read-write
WRS : WRS
bits : 18 - 19 (2 bit)
access : read-write
ALEW : ALEW
bits : 20 - 21 (2 bit)
access : read-write
RDR : RDR
bits : 24 - 26 (3 bit)
access : read-write
WRR : WRR
bits : 27 - 29 (3 bit)
access : read-write
CSR : CSR
bits : 30 - 31 (2 bit)
access : read-write
Chip Select and Wait Controller Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSW0 : CSW0
bits : 0 - 0 (1 bit)
access : read-write
CSW : CSW
bits : 1 - 2 (2 bit)
access : read-write
CSIW : CSIW
bits : 8 - 11 (4 bit)
access : read-write
WAIT : WAIT
bits : 12 - 12 (1 bit)
access : read-write
WSEL : WSEL
bits : 13 - 13 (1 bit)
access : read-write
RDS : RDS
bits : 16 - 17 (2 bit)
access : read-write
WRS : WRS
bits : 18 - 19 (2 bit)
access : read-write
ALEW : ALEW
bits : 20 - 21 (2 bit)
access : read-write
RDR : RDR
bits : 24 - 26 (3 bit)
access : read-write
WRR : WRR
bits : 27 - 29 (3 bit)
access : read-write
CSR : CSR
bits : 30 - 31 (2 bit)
access : read-write
Chip Select and Wait Controller Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSW0 : CSW0
bits : 0 - 0 (1 bit)
access : read-write
CSW : CSW
bits : 1 - 2 (2 bit)
access : read-write
CSIW : CSIW
bits : 8 - 11 (4 bit)
access : read-write
WAIT : WAIT
bits : 12 - 12 (1 bit)
access : read-write
WSEL : WSEL
bits : 13 - 13 (1 bit)
access : read-write
RDS : RDS
bits : 16 - 17 (2 bit)
access : read-write
WRS : WRS
bits : 18 - 19 (2 bit)
access : read-write
ALEW : ALEW
bits : 20 - 21 (2 bit)
access : read-write
RDR : RDR
bits : 24 - 26 (3 bit)
access : read-write
WRR : WRR
bits : 27 - 29 (3 bit)
access : read-write
CSR : CSR
bits : 30 - 31 (2 bit)
access : read-write
Chip Select and Wait Controller Register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSW0 : CSW0
bits : 0 - 0 (1 bit)
access : read-write
CSW : CSW
bits : 1 - 2 (2 bit)
access : read-write
CSIW : CSIW
bits : 8 - 11 (4 bit)
access : read-write
WAIT : WAIT
bits : 12 - 12 (1 bit)
access : read-write
WSEL : WSEL
bits : 13 - 13 (1 bit)
access : read-write
RDS : RDS
bits : 16 - 17 (2 bit)
access : read-write
WRS : WRS
bits : 18 - 19 (2 bit)
access : read-write
ALEW : ALEW
bits : 20 - 21 (2 bit)
access : read-write
RDR : RDR
bits : 24 - 26 (3 bit)
access : read-write
WRR : WRR
bits : 27 - 29 (3 bit)
access : read-write
CSR : CSR
bits : 30 - 31 (2 bit)
access : read-write
Clock output controlRegister
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKEN : CLKEN
bits : 0 - 0 (1 bit)
access : read-write
CLKDIV : CLKDIV
bits : 1 - 2 (2 bit)
access : read-write
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