\n

ADILV

Peripheral Memory Blocks

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

Registers

TRGSEL

EXCR


TRGSEL

Trigger Selection Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSEL TRGSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSELEN TRGSEL HPTRGSEL

TRGSELEN : TRGSELEN
bits : 0 - 0 (1 bit)
access : read-write

TRGSEL : TRGSEL
bits : 8 - 11 (4 bit)
access : read-write

HPTRGSEL : HPTRGSEL
bits : 12 - 15 (4 bit)
access : read-write


EXCR

Extencion channel setting Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXCR EXCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXEN EXSEL EXCR0 EXCR1

EXEN : EXEN
bits : 0 - 0 (1 bit)
access : read-write

EXSEL : EXSEL
bits : 1 - 3 (3 bit)
access : read-write

EXCR0 : EXCR0
bits : 4 - 4 (1 bit)
access : read-write

EXCR1 : EXCR1
bits : 5 - 5 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.