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SC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EN

BRCR

BRADD

MOD1

MOD2

RFC

TFC

RST

TST

FCNF

BUF

CR

MOD0


EN

SC Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIOE BRCKSEL

SIOE : SIOE
bits : 0 - 0 (1 bit)
access : read-write

BRCKSEL : BRCKSEL
bits : 1 - 1 (1 bit)
access : read-write


BRCR

SC Baud Rate Generator Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRCR BRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRS BRCK BRADDE

BRS : BRS
bits : 0 - 3 (4 bit)
access : read-write

BRCK : BRCK
bits : 4 - 5 (2 bit)
access : read-write

BRADDE : BRADDE
bits : 6 - 6 (1 bit)
access : read-write


BRADD

SC Baud Rate Generator Control Register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRADD BRADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRK

BRK : BRK
bits : 0 - 3 (4 bit)
access : read-write


MOD1

SC Mode Control Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD1 MOD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SINT TXE FDPX I2SC

SINT : SINT
bits : 1 - 3 (3 bit)
access : read-write

TXE : TXE
bits : 4 - 4 (1 bit)
access : read-write

FDPX : FDPX
bits : 5 - 6 (2 bit)
access : read-write

I2SC : I2SC
bits : 7 - 7 (1 bit)
access : read-write


MOD2

SC Mode Control Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD2 MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST WBUF DRCHG SBLEN TXRUN RBFLL TBEMP

SWRST : SWRST
bits : 0 - 1 (2 bit)
access : read-write

WBUF : WBUF
bits : 2 - 2 (1 bit)
access : read-write

DRCHG : DRCHG
bits : 3 - 3 (1 bit)
access : read-write

SBLEN : SBLEN
bits : 4 - 4 (1 bit)
access : read-write

TXRUN : TXRUN
bits : 5 - 5 (1 bit)
access : read-only

RBFLL : RBFLL
bits : 6 - 6 (1 bit)
access : read-only

TBEMP : TBEMP
bits : 7 - 7 (1 bit)
access : read-only


RFC

SC RX FIFO Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFC RFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIL RFIS RFCS

RIL : RIL
bits : 0 - 1 (2 bit)
access : read-write

RFIS : RFIS
bits : 6 - 6 (1 bit)
access : read-write

RFCS : RFCS
bits : 7 - 7 (1 bit)
access : write-only


TFC

SC TX FIFO Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFC TFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIL TFIS TFCS TBCLR

TIL : TIL
bits : 0 - 1 (2 bit)
access : read-write

TFIS : TFIS
bits : 6 - 6 (1 bit)
access : read-write

TFCS : TFCS
bits : 7 - 7 (1 bit)
access : write-only

TBCLR : TBCLR
bits : 8 - 8 (1 bit)
access : write-only


RST

SC RX FIFO Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RST RST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLVL ROR

RLVL : RLVL
bits : 0 - 2 (3 bit)
access : read-only

ROR : ROR
bits : 7 - 7 (1 bit)
access : read-only


TST

SC TX FIFO Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TST TST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLVL TUR

TLVL : TLVL
bits : 0 - 2 (3 bit)
access : read-only

TUR : TUR
bits : 7 - 7 (1 bit)
access : read-only


FCNF

SC FIFO Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCNF FCNF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNFG RXTXCNT RFIE TFIE RFST

CNFG : CNFG
bits : 0 - 0 (1 bit)
access : read-write

RXTXCNT : RXTXCNT
bits : 1 - 1 (1 bit)
access : read-write

RFIE : RFIE
bits : 2 - 2 (1 bit)
access : read-write

TFIE : TFIE
bits : 3 - 3 (1 bit)
access : read-write

RFST : RFST
bits : 4 - 4 (1 bit)
access : read-write


BUF

SC Buffer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUF BUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TB_RB

TB_RB : TB_RB
bits : 0 - 7 (8 bit)
access : read-write


CR

SC Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOC SCLKS FERR PERR OERR PE EVEN RB8 TIDLE TXDEMP EHOLD

IOC : IOC
bits : 0 - 0 (1 bit)
access : read-write

SCLKS : SCLKS
bits : 1 - 1 (1 bit)
access : read-write

FERR : FERR
bits : 2 - 2 (1 bit)
access : read-only

PERR : PERR
bits : 3 - 3 (1 bit)
access : read-only

OERR : OERR
bits : 4 - 4 (1 bit)
access : read-only

PE : PE
bits : 5 - 5 (1 bit)
access : read-write

EVEN : EVEN
bits : 6 - 6 (1 bit)
access : read-write

RB8 : RB8
bits : 7 - 7 (1 bit)
access : read-only

TIDLE : TIDLE
bits : 8 - 9 (2 bit)
access : read-write

TXDEMP : TXDEMP
bits : 10 - 10 (1 bit)
access : read-write

EHOLD : EHOLD
bits : 12 - 14 (3 bit)
access : read-write


MOD0

SC Mode Control Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD0 MOD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC SM WU RXE CTSE TB8

SC : SC
bits : 0 - 1 (2 bit)
access : read-write

SM : SM
bits : 2 - 3 (2 bit)
access : read-write

WU : WU
bits : 4 - 4 (1 bit)
access : read-write

RXE : RXE
bits : 5 - 5 (1 bit)
access : read-write

CTSE : CTSE
bits : 6 - 6 (1 bit)
access : read-write

TB8 : TB8
bits : 7 - 7 (1 bit)
access : read-write



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