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PH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

PUP

IE

CR


DATA

Port H Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14

PH0 : PH0
bits : 0 - 0 (1 bit)
access : read-write

PH1 : PH1
bits : 1 - 1 (1 bit)
access : read-write

PH2 : PH2
bits : 2 - 2 (1 bit)
access : read-write

PH3 : PH3
bits : 3 - 3 (1 bit)
access : read-write

PH4 : PH4
bits : 4 - 4 (1 bit)
access : read-write

PH5 : PH5
bits : 5 - 5 (1 bit)
access : read-write

PH6 : PH6
bits : 6 - 6 (1 bit)
access : read-write

PH7 : PH7
bits : 7 - 7 (1 bit)
access : read-write

PH8 : PH8
bits : 8 - 8 (1 bit)
access : read-write

PH9 : PH9
bits : 9 - 9 (1 bit)
access : read-write

PH10 : PH10
bits : 10 - 10 (1 bit)
access : read-write

PH11 : PH11
bits : 11 - 11 (1 bit)
access : read-write

PH12 : PH12
bits : 12 - 12 (1 bit)
access : read-write

PH13 : PH13
bits : 13 - 13 (1 bit)
access : read-write

PH14 : PH14
bits : 14 - 14 (1 bit)
access : read-write


PUP

Port H Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PH0UP PH1UP PH2UP PH3UP PH4UP PH5UP PH6UP PH7UP PH8UP PH9UP PH10UP PH11UP PH12UP PH13UP PH14UP

PH0UP : PH0UP
bits : 0 - 0 (1 bit)
access : read-write

PH1UP : PH1UP
bits : 1 - 1 (1 bit)
access : read-write

PH2UP : PH2UP
bits : 2 - 2 (1 bit)
access : read-write

PH3UP : PH3UP
bits : 3 - 3 (1 bit)
access : read-write

PH4UP : PH4UP
bits : 4 - 4 (1 bit)
access : read-write

PH5UP : PH5UP
bits : 5 - 5 (1 bit)
access : read-write

PH6UP : PH6UP
bits : 6 - 6 (1 bit)
access : read-write

PH7UP : PH7UP
bits : 7 - 7 (1 bit)
access : read-write

PH8UP : PH8UP
bits : 8 - 8 (1 bit)
access : read-write

PH9UP : PH9UP
bits : 9 - 9 (1 bit)
access : read-write

PH10UP : PH10UP
bits : 10 - 10 (1 bit)
access : read-write

PH11UP : PH11UP
bits : 11 - 11 (1 bit)
access : read-write

PH12UP : PH12UP
bits : 12 - 12 (1 bit)
access : read-write

PH13UP : PH13UP
bits : 13 - 13 (1 bit)
access : read-write

PH14UP : PH14UP
bits : 14 - 14 (1 bit)
access : read-write


IE

Port H Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PH0IE PH1IE PH2IE PH3IE PH4IE PH5IE PH6IE PH7IE PH8IE PH9IE PH10IE PH11IE PH12IE PH13IE PH14IE

PH0IE : PH0IE
bits : 0 - 0 (1 bit)
access : read-write

PH1IE : PH1IE
bits : 1 - 1 (1 bit)
access : read-write

PH2IE : PH2IE
bits : 2 - 2 (1 bit)
access : read-write

PH3IE : PH3IE
bits : 3 - 3 (1 bit)
access : read-write

PH4IE : PH4IE
bits : 4 - 4 (1 bit)
access : read-write

PH5IE : PH5IE
bits : 5 - 5 (1 bit)
access : read-write

PH6IE : PH6IE
bits : 6 - 6 (1 bit)
access : read-write

PH7IE : PH7IE
bits : 7 - 7 (1 bit)
access : read-write

PH8IE : PH8IE
bits : 8 - 8 (1 bit)
access : read-write

PH9IE : PH9IE
bits : 9 - 9 (1 bit)
access : read-write

PH10IE : PH10IE
bits : 10 - 10 (1 bit)
access : read-write

PH11IE : PH11IE
bits : 11 - 11 (1 bit)
access : read-write

PH12IE : PH12IE
bits : 12 - 12 (1 bit)
access : read-write

PH13IE : PH13IE
bits : 13 - 13 (1 bit)
access : read-write

PH14IE : PH14IE
bits : 14 - 14 (1 bit)
access : read-write


CR

Port H Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PH0C PH1C PH2C PH3C PH4C PH5C PH6C PH7C PH8C PH9C PH10C PH11C PH12C PH13C PH14C

PH0C : PH0C
bits : 0 - 0 (1 bit)
access : read-write

PH1C : PH1C
bits : 1 - 1 (1 bit)
access : read-write

PH2C : PH2C
bits : 2 - 2 (1 bit)
access : read-write

PH3C : PH3C
bits : 3 - 3 (1 bit)
access : read-write

PH4C : PH4C
bits : 4 - 4 (1 bit)
access : read-write

PH5C : PH5C
bits : 5 - 5 (1 bit)
access : read-write

PH6C : PH6C
bits : 6 - 6 (1 bit)
access : read-write

PH7C : PH7C
bits : 7 - 7 (1 bit)
access : read-write

PH8C : PH8C
bits : 8 - 8 (1 bit)
access : read-write

PH9C : PH9C
bits : 9 - 9 (1 bit)
access : read-write

PH10C : PH10C
bits : 10 - 10 (1 bit)
access : read-write

PH11C : PH11C
bits : 11 - 11 (1 bit)
access : read-write

PH12C : PH12C
bits : 12 - 12 (1 bit)
access : read-write

PH13C : PH13C
bits : 13 - 13 (1 bit)
access : read-write

PH14C : PH14C
bits : 14 - 14 (1 bit)
access : read-write



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