\n

CG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x54 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYSCR

FSYSMSKA

FSYSMSKB

PROTECT

OSCCR

IMCGA

IMCGB

IMCGC

IMCGD

IMCGE

ICRCG

RSTFLG

NMIFLG

STBYCR

PLLSEL


SYSCR

System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCR SYSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEAR PRCK FPSEL SCOSEL FCSTOP

GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write

PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write

FPSEL : FPSEL
bits : 12 - 12 (1 bit)
access : read-write

SCOSEL : SCOSEL
bits : 16 - 16 (1 bit)
access : read-write

FCSTOP : FCSTOP
bits : 20 - 20 (1 bit)
access : read-write


FSYSMSKA

fclk Supply Stop Register A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYSMSKA FSYSMSKA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORTH PORTJ PORTK TMRB0 TMRB1 TMRB2 TMRB3 TMRB4 TMRB5 TMRB6 TMRB7 TMRB8 TMRB9 TMRB10 TMRB11 TMRB12 TMRB13 TMRB14 TMRB15 MPT0 MPT1 TRACECLK

PORTA : PORTA
bits : 0 - 0 (1 bit)
access : read-write

PORTB : PORTB
bits : 1 - 1 (1 bit)
access : read-write

PORTC : PORTC
bits : 2 - 2 (1 bit)
access : read-write

PORTD : PORTD
bits : 3 - 3 (1 bit)
access : read-write

PORTE : PORTE
bits : 4 - 4 (1 bit)
access : read-write

PORTF : PORTF
bits : 5 - 5 (1 bit)
access : read-write

PORTG : PORTG
bits : 6 - 6 (1 bit)
access : read-write

PORTH : PORTH
bits : 7 - 7 (1 bit)
access : read-write

PORTJ : PORTJ
bits : 8 - 8 (1 bit)
access : read-write

PORTK : PORTK
bits : 9 - 9 (1 bit)
access : read-write

TMRB0 : TMRB0
bits : 13 - 13 (1 bit)
access : read-write

TMRB1 : TMRB1
bits : 14 - 14 (1 bit)
access : read-write

TMRB2 : TMRB2
bits : 15 - 15 (1 bit)
access : read-write

TMRB3 : TMRB3
bits : 16 - 16 (1 bit)
access : read-write

TMRB4 : TMRB4
bits : 17 - 17 (1 bit)
access : read-write

TMRB5 : TMRB5
bits : 18 - 18 (1 bit)
access : read-write

TMRB6 : TMRB6
bits : 19 - 19 (1 bit)
access : read-write

TMRB7 : TMRB7
bits : 20 - 20 (1 bit)
access : read-write

TMRB8 : TMRB8
bits : 21 - 21 (1 bit)
access : read-write

TMRB9 : TMRB9
bits : 22 - 22 (1 bit)
access : read-write

TMRB10 : TMRB10
bits : 23 - 23 (1 bit)
access : read-write

TMRB11 : TMRB11
bits : 24 - 24 (1 bit)
access : read-write

TMRB12 : TMRB12
bits : 25 - 25 (1 bit)
access : read-write

TMRB13 : TMRB13
bits : 26 - 26 (1 bit)
access : read-write

TMRB14 : TMRB14
bits : 27 - 27 (1 bit)
access : read-write

TMRB15 : TMRB15
bits : 28 - 28 (1 bit)
access : read-write

MPT0 : MPT0
bits : 29 - 29 (1 bit)
access : read-write

MPT1 : MPT1
bits : 30 - 30 (1 bit)
access : read-write

TRACECLK : TRACECLK
bits : 31 - 31 (1 bit)
access : read-write


FSYSMSKB

fclk Supply Stop Register B
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYSMSKB FSYSMSKB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIO0 SIO1 SIO2 SIO3 SIO4 SIO5 UART0 UART1 I2C0 I2C1 I2C2 I2C3 I2C4 SSP0 SSP1 SSP2 EBIF DMAA DMAB DMAC DMAIF ADC WDT OFD

SIO0 : SIO0
bits : 0 - 0 (1 bit)
access : read-write

SIO1 : SIO1
bits : 1 - 1 (1 bit)
access : read-write

SIO2 : SIO2
bits : 2 - 2 (1 bit)
access : read-write

SIO3 : SIO3
bits : 3 - 3 (1 bit)
access : read-write

SIO4 : SIO4
bits : 4 - 4 (1 bit)
access : read-write

SIO5 : SIO5
bits : 5 - 5 (1 bit)
access : read-write

UART0 : UART0
bits : 10 - 10 (1 bit)
access : read-write

UART1 : UART1
bits : 11 - 11 (1 bit)
access : read-write

I2C0 : I2C0
bits : 12 - 12 (1 bit)
access : read-write

I2C1 : I2C1
bits : 13 - 13 (1 bit)
access : read-write

I2C2 : I2C2
bits : 14 - 14 (1 bit)
access : read-write

I2C3 : I2C3
bits : 15 - 15 (1 bit)
access : read-write

I2C4 : I2C4
bits : 16 - 16 (1 bit)
access : read-write

SSP0 : SSP0
bits : 17 - 17 (1 bit)
access : read-write

SSP1 : SSP1
bits : 18 - 18 (1 bit)
access : read-write

SSP2 : SSP2
bits : 19 - 19 (1 bit)
access : read-write

EBIF : EBIF
bits : 20 - 20 (1 bit)
access : read-write

DMAA : DMAA
bits : 21 - 21 (1 bit)
access : read-write

DMAB : DMAB
bits : 22 - 22 (1 bit)
access : read-write

DMAC : DMAC
bits : 23 - 23 (1 bit)
access : read-write

DMAIF : DMAIF
bits : 24 - 24 (1 bit)
access : read-write

ADC : ADC
bits : 25 - 25 (1 bit)
access : read-write

WDT : WDT
bits : 26 - 26 (1 bit)
access : read-write

OFD : OFD
bits : 27 - 27 (1 bit)
access : read-write


PROTECT

Protect Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTECT PROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGPROTECT

CGPROTECT : CGPROTECT
bits : 0 - 7 (8 bit)
access : read-write


OSCCR

Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCR OSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XEN1 XEN2 XEN3 XTEN DRVOSCL OSCSEL OSCF HOSCON WUEON WUEF WUPSEL1 WUPSEL2 WUPTL WUPT

XEN1 : XEN1
bits : 0 - 0 (1 bit)
access : read-write

XEN2 : XEN2
bits : 1 - 1 (1 bit)
access : read-write

XEN3 : XEN3
bits : 2 - 2 (1 bit)
access : read-write

XTEN : XTEN
bits : 3 - 3 (1 bit)
access : read-write

DRVOSCL : DRVOSCL
bits : 7 - 7 (1 bit)
access : read-write

OSCSEL : OSCSEL
bits : 8 - 8 (1 bit)
access : read-write

OSCF : OSCF
bits : 9 - 9 (1 bit)
access : read-only

HOSCON : HOSCON
bits : 10 - 10 (1 bit)
access : read-write

WUEON : WUEON
bits : 14 - 14 (1 bit)
access : write-only

WUEF : WUEF
bits : 15 - 15 (1 bit)
access : read-only

WUPSEL1 : WUPSEL1
bits : 16 - 16 (1 bit)
access : read-write

WUPSEL2 : WUPSEL2
bits : 17 - 17 (1 bit)
access : read-write

WUPTL : WUPTL
bits : 18 - 19 (2 bit)
access : read-write

WUPT : WUPT
bits : 20 - 31 (12 bit)
access : read-write


IMCGA

CG Interrupt Mode Control Register A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGA IMCGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT00EN EMST00 EMCG00 INT01EN EMST01 EMCG01 INT02EN EMST02 EMCG02 INT03EN EMST03 EMCG03

INT00EN : INT00EN
bits : 0 - 0 (1 bit)
access : read-write

EMST00 : EMST00
bits : 2 - 3 (2 bit)
access : read-only

EMCG00 : EMCG00
bits : 4 - 6 (3 bit)
access : read-write

INT01EN : INT01EN
bits : 8 - 8 (1 bit)
access : read-write

EMST01 : EMST01
bits : 10 - 11 (2 bit)
access : read-only

EMCG01 : EMCG01
bits : 12 - 14 (3 bit)
access : read-write

INT02EN : INT02EN
bits : 16 - 16 (1 bit)
access : read-write

EMST02 : EMST02
bits : 18 - 19 (2 bit)
access : read-only

EMCG02 : EMCG02
bits : 20 - 22 (3 bit)
access : read-write

INT03EN : INT03EN
bits : 24 - 24 (1 bit)
access : read-write

EMST03 : EMST03
bits : 26 - 27 (2 bit)
access : read-only

EMCG03 : EMCG03
bits : 28 - 30 (3 bit)
access : read-write


IMCGB

CG Interrupt Mode Control Register B
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGB IMCGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT04EN EMST04 EMCG04 INT05EN EMST05 EMCG05 INT06EN EMST06 EMCG06 INT07EN EMST07 EMCG07

INT04EN : INT04EN
bits : 0 - 0 (1 bit)
access : read-write

EMST04 : EMST04
bits : 2 - 3 (2 bit)
access : read-only

EMCG04 : EMCG04
bits : 4 - 6 (3 bit)
access : read-write

INT05EN : INT05EN
bits : 8 - 8 (1 bit)
access : read-write

EMST05 : EMST05
bits : 10 - 11 (2 bit)
access : read-only

EMCG05 : EMCG05
bits : 12 - 14 (3 bit)
access : read-write

INT06EN : INT06EN
bits : 16 - 16 (1 bit)
access : read-write

EMST06 : EMST06
bits : 18 - 19 (2 bit)
access : read-only

EMCG06 : EMCG06
bits : 20 - 22 (3 bit)
access : read-write

INT07EN : INT07EN
bits : 24 - 24 (1 bit)
access : read-write

EMST07 : EMST07
bits : 26 - 27 (2 bit)
access : read-only

EMCG07 : EMCG07
bits : 28 - 30 (3 bit)
access : read-write


IMCGC

CG Interrupt Mode Control Register C
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGC IMCGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT08EN EMST08 EMCG08 INT09EN EMST09 EMCG09 INT0AEN EMST0A EMCG0A INT0BEN EMST0B EMCG0B

INT08EN : INT08EN
bits : 0 - 0 (1 bit)
access : read-write

EMST08 : EMST08
bits : 2 - 3 (2 bit)
access : read-only

EMCG08 : EMCG08
bits : 4 - 6 (3 bit)
access : read-write

INT09EN : INT09EN
bits : 8 - 8 (1 bit)
access : read-write

EMST09 : EMST09
bits : 10 - 11 (2 bit)
access : read-only

EMCG09 : EMCG09
bits : 12 - 14 (3 bit)
access : read-write

INT0AEN : INT0AEN
bits : 16 - 16 (1 bit)
access : read-write

EMST0A : EMST0A
bits : 18 - 19 (2 bit)
access : read-only

EMCG0A : EMCG0A
bits : 20 - 22 (3 bit)
access : read-write

INT0BEN : INT0BEN
bits : 24 - 24 (1 bit)
access : read-write

EMST0B : EMST0B
bits : 26 - 27 (2 bit)
access : read-only

EMCG0B : EMCG0B
bits : 28 - 30 (3 bit)
access : read-write


IMCGD

CG Interrupt Mode Control Register D
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGD IMCGD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT0CEN EMST0C EMCG0C INT0DEN EMST0D EMCG0D INT0EEN EMST0E EMCG0E INT0FEN EMST0F EMCG0F

INT0CEN : INT0CEN
bits : 0 - 0 (1 bit)
access : read-write

EMST0C : EMST0C
bits : 2 - 3 (2 bit)
access : read-only

EMCG0C : EMCG0C
bits : 4 - 6 (3 bit)
access : read-write

INT0DEN : INT0DEN
bits : 8 - 8 (1 bit)
access : read-write

EMST0D : EMST0D
bits : 10 - 11 (2 bit)
access : read-only

EMCG0D : EMCG0D
bits : 12 - 14 (3 bit)
access : read-write

INT0EEN : INT0EEN
bits : 16 - 16 (1 bit)
access : read-write

EMST0E : EMST0E
bits : 18 - 19 (2 bit)
access : read-only

EMCG0E : EMCG0E
bits : 20 - 22 (3 bit)
access : read-write

INT0FEN : INT0FEN
bits : 24 - 24 (1 bit)
access : read-write

EMST0F : EMST0F
bits : 26 - 27 (2 bit)
access : read-only

EMCG0F : EMCG0F
bits : 28 - 30 (3 bit)
access : read-write


IMCGE

CG Interrupt Mode Control Register E
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGE IMCGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT10EN EMST10 EMCG10 INT11EN EMST11 EMCG11 INT12EN EMST12 EMCG12 INT13EN EMST13 EMCG13

INT10EN : INT10EN
bits : 0 - 0 (1 bit)
access : read-write

EMST10 : EMST10
bits : 2 - 3 (2 bit)
access : read-only

EMCG10 : EMCG10
bits : 4 - 6 (3 bit)
access : read-write

INT11EN : INT11EN
bits : 8 - 8 (1 bit)
access : read-write

EMST11 : EMST11
bits : 10 - 11 (2 bit)
access : read-only

EMCG11 : EMCG11
bits : 12 - 14 (3 bit)
access : read-write

INT12EN : INT12EN
bits : 16 - 16 (1 bit)
access : read-write

EMST12 : EMST12
bits : 18 - 19 (2 bit)
access : read-only

EMCG12 : EMCG12
bits : 20 - 22 (3 bit)
access : read-write

INT13EN : INT13EN
bits : 24 - 24 (1 bit)
access : read-write

EMST13 : EMST13
bits : 26 - 27 (2 bit)
access : read-only

EMCG13 : EMCG13
bits : 28 - 30 (3 bit)
access : read-write


ICRCG

CG Interrupt Request Clear Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICRCG ICRCG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICRCG

ICRCG : ICRCG
bits : 0 - 4 (5 bit)
access : write-only


RSTFLG

Reset Flag Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTFLG RSTFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINRSTF OSCFLF WDTRSTF BUPRSTF SYSRSTF OFDRSTF LVDRSTF

PINRSTF : PINRSTF
bits : 0 - 0 (1 bit)
access : read-write

OSCFLF : OSCFLF
bits : 1 - 1 (1 bit)
access : read-only

WDTRSTF : WDTRSTF
bits : 2 - 2 (1 bit)
access : read-write

BUPRSTF : BUPRSTF
bits : 3 - 3 (1 bit)
access : read-write

SYSRSTF : SYSRSTF
bits : 4 - 4 (1 bit)
access : read-write

OFDRSTF : OFDRSTF
bits : 5 - 5 (1 bit)
access : read-write

LVDRSTF : LVDRSTF
bits : 6 - 6 (1 bit)
access : read-write


NMIFLG

NMI Flag Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMIFLG NMIFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIFLG0 NMIFLG1 NMIFLG2 NMIFLG4

NMIFLG0 : NMIFLG0
bits : 0 - 0 (1 bit)
access : read-only

NMIFLG1 : NMIFLG1
bits : 1 - 1 (1 bit)
access : read-only

NMIFLG2 : NMIFLG2
bits : 2 - 2 (1 bit)
access : read-only

NMIFLG4 : NMIFLG4
bits : 4 - 4 (1 bit)
access : read-only


STBYCR

Standby Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STBYCR STBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY PTKEEP

STBY : STBY
bits : 0 - 2 (3 bit)
access : read-write

PTKEEP : PTKEEP
bits : 17 - 17 (1 bit)
access : read-write


PLLSEL

PLL Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSEL PLLSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSET PLLON PLLSEL PLLST

PLLSET : PLLSET
bits : 1 - 15 (15 bit)
access : read-write

PLLON : PLLON
bits : 16 - 16 (1 bit)
access : read-write

PLLSEL : PLLSEL
bits : 17 - 17 (1 bit)
access : read-write

PLLST : PLLST
bits : 18 - 18 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.