\n

LVD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR0

CR1


CR0

LVD detection control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN LVL INTEN RSTEN ST

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

LVL : LVL
bits : 1 - 3 (3 bit)
access : read-write

INTEN : INTEN
bits : 5 - 5 (1 bit)
access : read-write

RSTEN : RSTEN
bits : 6 - 6 (1 bit)
access : read-write

ST : ST
bits : 7 - 7 (1 bit)
access : read-only


CR1

LVD detection control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN LVL INTEN RSTEN ST

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

LVL : LVL
bits : 1 - 3 (3 bit)
access : read-write

INTEN : INTEN
bits : 5 - 5 (1 bit)
access : read-write

RSTEN : RSTEN
bits : 6 - 6 (1 bit)
access : read-write

ST : ST
bits : 7 - 7 (1 bit)
access : read-only



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