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AD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x74 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x54 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

CLK

MOD3

MOD4

MOD5

MOD6

CMPCR0

CMPCR1

CMP0

CMP1

REG00

REG01

REG02

MOD0

REG03

REG04

REG05

REG06

REG07

REGSP

MOD1

MOD2


CLK

Conversion Clock Setting Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCLK ADSH

ADCLK : ADCLK
bits : 0 - 2 (3 bit)
access : read-write

ADSH : ADSH
bits : 4 - 7 (4 bit)
access : read-write


MOD3

Mode Control Register3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD3 MOD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCAN REPEAT ITM

SCAN : SCAN
bits : 0 - 0 (1 bit)
access : read-write

REPEAT : REPEAT
bits : 1 - 1 (1 bit)
access : read-write

ITM : ITM
bits : 4 - 6 (3 bit)
access : read-write


MOD4

Mode Control Register4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD4 MOD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCANSTA SCANAREA

SCANSTA : SCANSTA
bits : 0 - 3 (4 bit)
access : read-write

SCANAREA : SCANAREA
bits : 4 - 7 (4 bit)
access : read-write


MOD5

Mode Control Register5
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MOD5 MOD5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBF EOCF HPADBF HPEOCF

ADBF : ADBF
bits : 0 - 0 (1 bit)
access : read-only

EOCF : EOCF
bits : 1 - 1 (1 bit)
access : read-only

HPADBF : HPADBF
bits : 2 - 2 (1 bit)
access : read-only

HPEOCF : HPEOCF
bits : 3 - 3 (1 bit)
access : read-only


MOD6

Mode Control Register6
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MOD6 MOD6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRST

ADRST : ADRST
bits : 0 - 1 (2 bit)
access : write-only


CMPCR0

Monitoring Interrupt Control Register0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCR0 CMPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINS0 ADBIG0 CMPCOND0 CMP0EN CMPCNT0

AINS0 : AINS0
bits : 0 - 3 (4 bit)
access : read-write

ADBIG0 : ADBIG0
bits : 4 - 4 (1 bit)
access : read-write

CMPCOND0 : CMPCOND0
bits : 5 - 5 (1 bit)
access : read-write

CMP0EN : CMP0EN
bits : 7 - 7 (1 bit)
access : read-write

CMPCNT0 : CMPCNT0
bits : 8 - 11 (4 bit)
access : read-write


CMPCR1

Monitoring Interrupt Control Register1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCR1 CMPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINS1 ADBIG1 CMPCOND1 CMP1EN CMPCNT1

AINS1 : AINS1
bits : 0 - 3 (4 bit)
access : read-write

ADBIG1 : ADBIG1
bits : 4 - 4 (1 bit)
access : read-write

CMPCOND1 : CMPCOND1
bits : 5 - 5 (1 bit)
access : read-write

CMP1EN : CMP1EN
bits : 7 - 7 (1 bit)
access : read-write

CMPCNT1 : CMPCNT1
bits : 8 - 11 (4 bit)
access : read-write


CMP0

Conversion Result Compare Register0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP0 CMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0CMP

AD0CMP : AD0CMP
bits : 0 - 11 (12 bit)
access : read-write


CMP1

Conversion Result Compare Register1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP1 CMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD1CMP

AD1CMP : AD1CMP
bits : 0 - 11 (12 bit)
access : read-write


REG00

Conversion Result Store Register0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG00 REG00 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR ADRF ADOVRF ADRF_MIR ADOVRF_MIR ADR_MIR

ADR : ADR
bits : 0 - 11 (12 bit)
access : read-only

ADRF : ADRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRF : ADOVRF
bits : 13 - 13 (1 bit)
access : read-only

ADRF_MIR : ADRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRF_MIR : ADOVRF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADR_MIR : ADR_MIR
bits : 20 - 31 (12 bit)
access : read-only


REG01

Conversion Result Store Register1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG01 REG01 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR ADRF ADOVRF ADRF_MIR ADOVRF_MIR ADR_MIR

ADR : ADR
bits : 0 - 11 (12 bit)
access : read-only

ADRF : ADRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRF : ADOVRF
bits : 13 - 13 (1 bit)
access : read-only

ADRF_MIR : ADRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRF_MIR : ADOVRF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADR_MIR : ADR_MIR
bits : 20 - 31 (12 bit)
access : read-only


REG02

Conversion Result Store Register2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG02 REG02 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR ADRF ADOVRF ADRF_MIR ADOVRF_MIR ADR_MIR

ADR : ADR
bits : 0 - 11 (12 bit)
access : read-only

ADRF : ADRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRF : ADOVRF
bits : 13 - 13 (1 bit)
access : read-only

ADRF_MIR : ADRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRF_MIR : ADOVRF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADR_MIR : ADR_MIR
bits : 20 - 31 (12 bit)
access : read-only


MOD0

Mode Control Register0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MOD0 MOD0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADS HPADS

ADS : ADS
bits : 0 - 0 (1 bit)
access : write-only

HPADS : HPADS
bits : 1 - 1 (1 bit)
access : write-only


REG03

Conversion Result Store Register3
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG03 REG03 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR ADRF ADOVRF ADRF_MIR ADOVRF_MIR ADR_MIR

ADR : ADR
bits : 0 - 11 (12 bit)
access : read-only

ADRF : ADRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRF : ADOVRF
bits : 13 - 13 (1 bit)
access : read-only

ADRF_MIR : ADRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRF_MIR : ADOVRF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADR_MIR : ADR_MIR
bits : 20 - 31 (12 bit)
access : read-only


REG04

Conversion Result Store Register4
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG04 REG04 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR ADRF ADOVRF ADRF_MIR ADOVRF_MIR ADR_MIR

ADR : ADR
bits : 0 - 11 (12 bit)
access : read-only

ADRF : ADRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRF : ADOVRF
bits : 13 - 13 (1 bit)
access : read-only

ADRF_MIR : ADRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRF_MIR : ADOVRF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADR_MIR : ADR_MIR
bits : 20 - 31 (12 bit)
access : read-only


REG05

Conversion Result Store Register5
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG05 REG05 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR ADRF ADOVRF ADRF_MIR ADOVRF_MIR ADR_MIR

ADR : ADR
bits : 0 - 11 (12 bit)
access : read-only

ADRF : ADRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRF : ADOVRF
bits : 13 - 13 (1 bit)
access : read-only

ADRF_MIR : ADRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRF_MIR : ADOVRF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADR_MIR : ADR_MIR
bits : 20 - 31 (12 bit)
access : read-only


REG06

Conversion Result Store Register6
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG06 REG06 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR ADRF ADOVRF ADRF_MIR ADOVRF_MIR ADR_MIR

ADR : ADR
bits : 0 - 11 (12 bit)
access : read-only

ADRF : ADRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRF : ADOVRF
bits : 13 - 13 (1 bit)
access : read-only

ADRF_MIR : ADRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRF_MIR : ADOVRF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADR_MIR : ADR_MIR
bits : 20 - 31 (12 bit)
access : read-only


REG07

Conversion Result Store Register7
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REG07 REG07 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR ADRF ADOVRF ADRF_MIR ADOVRF_MIR ADR_MIR

ADR : ADR
bits : 0 - 11 (12 bit)
access : read-only

ADRF : ADRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRF : ADOVRF
bits : 13 - 13 (1 bit)
access : read-only

ADRF_MIR : ADRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRF_MIR : ADOVRF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADR_MIR : ADR_MIR
bits : 20 - 31 (12 bit)
access : read-only


REGSP

Highest Priority Conversion Result Store Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REGSP REGSP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSPR ADSPRF ADOVRSPF ADSPRF_MIR ADOVRSPF_MIR ADSPR_MIR

ADSPR : ADSPR
bits : 0 - 11 (12 bit)
access : read-only

ADSPRF : ADSPRF
bits : 12 - 12 (1 bit)
access : read-only

ADOVRSPF : ADOVRSPF
bits : 13 - 13 (1 bit)
access : read-only

ADSPRF_MIR : ADSPRF_MIR
bits : 16 - 16 (1 bit)
access : read-only

ADOVRSPF_MIR : ADOVRSPF_MIR
bits : 17 - 17 (1 bit)
access : read-only

ADSPR_MIR : ADSPR_MIR
bits : 20 - 31 (12 bit)
access : read-only


MOD1

Mode Control Register1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD1 MOD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADHWE ADHWS HPADHWE HPADHWS RCUT I2AD DACON

ADHWE : ADHWE
bits : 0 - 0 (1 bit)
access : read-write

ADHWS : ADHWS
bits : 1 - 1 (1 bit)
access : read-write

HPADHWE : HPADHWE
bits : 2 - 2 (1 bit)
access : read-write

HPADHWS : HPADHWS
bits : 3 - 3 (1 bit)
access : read-write

RCUT : RCUT
bits : 5 - 5 (1 bit)
access : read-write

I2AD : I2AD
bits : 6 - 6 (1 bit)
access : read-write

DACON : DACON
bits : 7 - 7 (1 bit)
access : read-write


MOD2

Mode Control Register2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD2 MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCH HPADCH

ADCH : ADCH
bits : 0 - 3 (4 bit)
access : read-write

HPADCH : HPADCH
bits : 4 - 7 (4 bit)
access : read-write



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