\n

PL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

FR3

FR4

FR5

FR6

OD

PUP

IE

CR


DATA

Port L Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0 PL1 PL2 PL3

PL0 : PL0
bits : 0 - 0 (1 bit)
access : read-write

PL1 : PL1
bits : 1 - 1 (1 bit)
access : read-write

PL2 : PL2
bits : 2 - 2 (1 bit)
access : read-write

PL3 : PL3
bits : 3 - 3 (1 bit)
access : read-write


FR3

Port L Function Register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR3 FR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0F3 PL1F3 PL2F3 PL3F3

PL0F3 : PL0F3
bits : 0 - 0 (1 bit)
access : read-write

PL1F3 : PL1F3
bits : 1 - 1 (1 bit)
access : read-write

PL2F3 : PL2F3
bits : 2 - 2 (1 bit)
access : read-write

PL3F3 : PL3F3
bits : 3 - 3 (1 bit)
access : read-write


FR4

Port L Function Register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR4 FR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0F4 PL2F4 PL3F4

PL0F4 : PL0F4
bits : 0 - 0 (1 bit)
access : read-write

PL2F4 : PL2F4
bits : 2 - 2 (1 bit)
access : read-write

PL3F4 : PL3F4
bits : 3 - 3 (1 bit)
access : read-write


FR5

Port L Function Register 5
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR5 FR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL1F5 PL2F5 PL3F5

PL1F5 : PL1F5
bits : 1 - 1 (1 bit)
access : read-write

PL2F5 : PL2F5
bits : 2 - 2 (1 bit)
access : read-write

PL3F5 : PL3F5
bits : 3 - 3 (1 bit)
access : read-write


FR6

Port L Function Register 6
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR6 FR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL3F6

PL3F6 : PL3F6
bits : 3 - 3 (1 bit)
access : read-write


OD

Port L Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0OD PL1OD PL2OD PL3OD

PL0OD : PL0OD
bits : 0 - 0 (1 bit)
access : read-write

PL1OD : PL1OD
bits : 1 - 1 (1 bit)
access : read-write

PL2OD : PL2OD
bits : 2 - 2 (1 bit)
access : read-write

PL3OD : PL3OD
bits : 3 - 3 (1 bit)
access : read-write


PUP

Port L Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0UP PL1UP PL2UP PL3UP

PL0UP : PL0UP
bits : 0 - 0 (1 bit)
access : read-write

PL1UP : PL1UP
bits : 1 - 1 (1 bit)
access : read-write

PL2UP : PL2UP
bits : 2 - 2 (1 bit)
access : read-write

PL3UP : PL3UP
bits : 3 - 3 (1 bit)
access : read-write


IE

Port L Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0IE PL1IE PL2IE PL3IE

PL0IE : PL0IE
bits : 0 - 0 (1 bit)
access : read-write

PL1IE : PL1IE
bits : 1 - 1 (1 bit)
access : read-write

PL2IE : PL2IE
bits : 2 - 2 (1 bit)
access : read-write

PL3IE : PL3IE
bits : 3 - 3 (1 bit)
access : read-write


CR

Port L Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0C PL1C PL2C PL3C

PL0C : PL0C
bits : 0 - 0 (1 bit)
access : read-write

PL1C : PL1C
bits : 1 - 1 (1 bit)
access : read-write

PL2C : PL2C
bits : 2 - 2 (1 bit)
access : read-write

PL3C : PL3C
bits : 3 - 3 (1 bit)
access : read-write



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