\n

TB0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EN

FFCR

ST

IM

UC

RG0

RG1

CP0

CP1

RUN

CR

MOD


EN

TB Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBHALT TBEN

TBHALT : TBHALT
bits : 6 - 6 (1 bit)
access : read-write

TBEN : TBEN
bits : 7 - 7 (1 bit)
access : read-write


FFCR

TB Flip-Flop Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FFCR FFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBFF0C TBE0T1 TBE1T1 TBC0T1 TBC1T1

TBFF0C : TBFF0C
bits : 0 - 1 (2 bit)
access : read-write

TBE0T1 : TBE0T1
bits : 2 - 2 (1 bit)
access : read-write

TBE1T1 : TBE1T1
bits : 3 - 3 (1 bit)
access : read-write

TBC0T1 : TBC0T1
bits : 4 - 4 (1 bit)
access : read-write

TBC1T1 : TBC1T1
bits : 5 - 5 (1 bit)
access : read-write


ST

TB Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ST ST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTTB0 INTTB1 INTTBOF

INTTB0 : INTTB0
bits : 0 - 0 (1 bit)
access : read-only

INTTB1 : INTTB1
bits : 1 - 1 (1 bit)
access : read-only

INTTBOF : INTTBOF
bits : 2 - 2 (1 bit)
access : read-only


IM

TB Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBIM0 TBIM1 TBIMOF

TBIM0 : TBIM0
bits : 0 - 0 (1 bit)
access : read-write

TBIM1 : TBIM1
bits : 1 - 1 (1 bit)
access : read-write

TBIMOF : TBIMOF
bits : 2 - 2 (1 bit)
access : read-write


UC

TB Up-counter Capture Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UC UC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBUC

TBUC : TBUC
bits : 0 - 15 (16 bit)
access : read-only


RG0

TB RG0 Timer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG0 RG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRG0

TBRG0 : TBRG0
bits : 0 - 15 (16 bit)
access : read-write


RG1

TB RG1 Timer Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG1 RG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRG1

TBRG1 : TBRG1
bits : 0 - 15 (16 bit)
access : read-write


CP0

TB CP0 Capture Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0 CP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCP0

TBCP0 : TBCP0
bits : 0 - 15 (16 bit)
access : read-only


CP1

TB CP1 Capture Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP1 CP1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCP1

TBCP1 : TBCP1
bits : 0 - 15 (16 bit)
access : read-only


RUN

TB RUN Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RUN RUN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRUN TBPRUN

TBRUN : TBRUN
bits : 0 - 0 (1 bit)
access : read-write

TBPRUN : TBPRUN
bits : 2 - 2 (1 bit)
access : read-write


CR

TB Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSSEL TRGSEL I2TB TBSYNC TBWBF

CSSEL : CSSEL
bits : 0 - 0 (1 bit)
access : read-write

TRGSEL : TRGSEL
bits : 1 - 1 (1 bit)
access : read-write

I2TB : I2TB
bits : 3 - 3 (1 bit)
access : read-write

TBSYNC : TBSYNC
bits : 5 - 5 (1 bit)
access : read-write

TBWBF : TBWBF
bits : 7 - 7 (1 bit)
access : read-write


MOD

TB Mode Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCLK TBCLE TBCP TBCPM

TBCLK : TBCLK
bits : 0 - 2 (3 bit)
access : read-write

TBCLE : TBCLE
bits : 3 - 3 (1 bit)
access : read-write

TBCP : TBCP
bits : 6 - 6 (1 bit)
access : write-only

TBCPM : TBCPM
bits : 8 - 10 (3 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.