\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection : not protected
Port L Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PL0 : PL0
bits : 0 - 0 (1 bit)
access : read-write
PL1 : PL1
bits : 1 - 1 (1 bit)
access : read-write
Port L Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PL0OD : PL0OD
bits : 0 - 0 (1 bit)
access : read-write
PL1OD : PL1OD
bits : 1 - 1 (1 bit)
access : read-write
Port L Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PL0UP : PL0UP
bits : 0 - 0 (1 bit)
access : read-write
PL1UP : PL1UP
bits : 1 - 1 (1 bit)
access : read-write
Port L Pull-down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PL0DN : PL0DN
bits : 0 - 0 (1 bit)
access : read-write
PL1DN : PL1DN
bits : 1 - 1 (1 bit)
access : read-write
Port L Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PL0IE : PL0IE
bits : 0 - 0 (1 bit)
access : read-write
PL1IE : PL1IE
bits : 1 - 1 (1 bit)
access : read-write
Port L Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PL0C : PL0C
bits : 0 - 0 (1 bit)
access : read-write
PL1C : PL1C
bits : 1 - 1 (1 bit)
access : read-write
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