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IA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1 Bytes (0x0)
size : 0x1F byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x11 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x51 Bytes (0x0)
size : 0x9 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INC00

IMC00

IMC01

IMC02

IMC03

IMC04

IMC05

IMC06

IMC07

IMC08

IMC09

IMC10

IMC11

IMC12

IMC13

IMC14

IMC15

IMC16

IMC17

IMC18

IMC19

IMC20

IMC21

IMC22

IMC23

IMC24

IMC25

IMC26

IMC27

IMC28

IMC29

IMC30

IMC31

IMC49

IMC50

IMC51

IMC52

IMC53

IMC54

IMC55

IMC56

IMC57


INC00

Non Maskable Interrupu Mode Control Register A 00
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INC00 INC00 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTNFLG INTNCLR

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC00

Interrupu Mode Control Register A 00
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC00 IMC00 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC01

Interrupu Mode Control Register A 01
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC01 IMC01 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC02

Interrupu Mode Control Register A 02
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC02 IMC02 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC03

Interrupu Mode Control Register A 03
address_offset : 0x23 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC03 IMC03 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC04

Interrupu Mode Control Register A 04
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC04 IMC04 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC05

Interrupu Mode Control Register A 05
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC05 IMC05 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC06

Interrupu Mode Control Register A 06
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC06 IMC06 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC07

Interrupu Mode Control Register A 07
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC07 IMC07 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC08

Interrupu Mode Control Register A 08
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC08 IMC08 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC09

Interrupu Mode Control Register A 09
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC09 IMC09 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC10

Interrupu Mode Control Register A 10
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC10 IMC10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC11

Interrupu Mode Control Register A 11
address_offset : 0x2B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC11 IMC11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC12

Interrupu Mode Control Register A 12
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC12 IMC12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC13

Interrupu Mode Control Register A 13
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC13 IMC13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC14

Interrupu Mode Control Register A 14
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC14 IMC14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC15

Interrupu Mode Control Register A 15
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC15 IMC15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC16

Interrupu Mode Control Register A 16
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC16 IMC16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC17

Interrupu Mode Control Register A 17
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC17 IMC17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC18

Interrupu Mode Control Register A 18
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC18 IMC18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC19

Interrupu Mode Control Register A 19
address_offset : 0x33 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC19 IMC19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC20

Interrupu Mode Control Register A 20
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC20 IMC20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC21

Interrupu Mode Control Register A 21
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC21 IMC21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC22

Interrupu Mode Control Register A 22
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC22 IMC22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC23

Interrupu Mode Control Register A 23
address_offset : 0x37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC23 IMC23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC24

Interrupu Mode Control Register A 24
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC24 IMC24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC25

Interrupu Mode Control Register A 25
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC25 IMC25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC26

Interrupu Mode Control Register A 26
address_offset : 0x3A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC26 IMC26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC27

Interrupu Mode Control Register A 27
address_offset : 0x3B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC27 IMC27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC28

Interrupu Mode Control Register A 28
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC28 IMC28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC29

Interrupu Mode Control Register A 29
address_offset : 0x3D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC29 IMC29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC30

Interrupu Mode Control Register A 30
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC30 IMC30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC31

Interrupu Mode Control Register A 31
address_offset : 0x3F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC31 IMC31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC49

Interrupu Mode Control Register A 49
address_offset : 0x51 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC49 IMC49 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC50

Interrupu Mode Control Register A 50
address_offset : 0x52 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC50 IMC50 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC51

Interrupu Mode Control Register A 51
address_offset : 0x53 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC51 IMC51 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC52

Interrupu Mode Control Register A 52
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC52 IMC52 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC53

Interrupu Mode Control Register A 53
address_offset : 0x55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC53 IMC53 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC54

Interrupu Mode Control Register A 54
address_offset : 0x56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC54 IMC54 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC55

Interrupu Mode Control Register A 55
address_offset : 0x57 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC55 IMC55 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC56

Interrupu Mode Control Register A 56
address_offset : 0x58 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC56 IMC56 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only


IMC57

Interrupu Mode Control Register A 57
address_offset : 0x59 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC57 IMC57 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTEN INTMODE INTPFLG INTNFLG INTPCLR INTNCLR

INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-write

INTMODE : INTMODE
bits : 1 - 3 (3 bit)
access : read-write

INTPFLG : INTPFLG
bits : 4 - 4 (1 bit)
access : read-only

INTNFLG : INTNFLG
bits : 5 - 5 (1 bit)
access : read-only

INTPCLR : INTPCLR
bits : 6 - 6 (1 bit)
access : write-only

INTNCLR : INTNCLR
bits : 7 - 7 (1 bit)
access : write-only



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