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LVD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

CR2

LVL1

LVL2

SR


CR1

LVD Control register1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LVDNEN LVSDEN LVDSEL SELVD

LVDNEN : LVDNEN
bits : 0 - 0 (1 bit)
access : read-write

LVSDEN : LVSDEN
bits : 1 - 1 (1 bit)
access : read-write

LVDSEL : LVDSEL
bits : 4 - 4 (1 bit)
access : read-write

SELVD : SELVD
bits : 7 - 7 (1 bit)
access : read-write


CR2

LVD Control register2
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LVDOEN

LVDOEN : LVDOEN
bits : 0 - 0 (1 bit)
access : read-write


LVL1

LVD detection voltage select register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVL1 LVL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LVDNLVL

LVDNLVL : LVDNLVL
bits : 0 - 3 (4 bit)
access : read-write


LVL2

LVD detection voltage select register 2
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVL2 LVL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LVDSLVL

LVDSLVL : LVDSLVL
bits : 0 - 3 (4 bit)
access : read-write


SR

LVD status register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LVDNS LVDSS

LVDNS : LVDNS
bits : 0 - 0 (1 bit)
access : read-only

LVDSS : LVDSS
bits : 1 - 1 (1 bit)
access : read-only



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