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CG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x5C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x68 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x48 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x54 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

PROTECT

OCR

PLL0SEL

WUPHCR

WUPLCR

OSCCR

FSYSMENA

FSYSMENB

FSYSENA

SPCLKEN

EXTEND2

SYSCR

STBYCR


PROTECT

Protect Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTECT PROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT

PROTECT : PROTECT
bits : 0 - 7 (8 bit)
access : read-write


OCR

SCOUT Output Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCR OCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCOEN SCOSEL SCODIV

SCOEN : SCOEN
bits : 0 - 0 (1 bit)
access : read-write

SCOSEL : SCOSEL
bits : 1 - 3 (3 bit)
access : read-write

SCODIV : SCODIV
bits : 4 - 6 (3 bit)
access : read-write


PLL0SEL

PLL Selection Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL0SEL PLL0SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL0ON PLL0SEL PLL0ST PLL0SET

PLL0ON : PLL0ON
bits : 0 - 0 (1 bit)
access : read-write

PLL0SEL : PLL0SEL
bits : 1 - 1 (1 bit)
access : read-write

PLL0ST : PLL0ST
bits : 2 - 2 (1 bit)
access : read-only

PLL0SET : PLL0SET
bits : 8 - 31 (24 bit)
access : read-write


WUPHCR

High OSC Warming-up Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUPHCR WUPHCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUON WUEF WUCLK WUPT

WUON : WUON
bits : 0 - 0 (1 bit)
access : write-only

WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only

WUCLK : WUCLK
bits : 8 - 8 (1 bit)
access : read-write

WUPT : WUPT
bits : 16 - 31 (16 bit)
access : read-write


WUPLCR

Low OSC Warming-up Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUPLCR WUPLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WULON WULEF WUPTL

WULON : WULON
bits : 0 - 0 (1 bit)
access : write-only

WULEF : WULEF
bits : 1 - 1 (1 bit)
access : read-only

WUPTL : WUPTL
bits : 8 - 26 (19 bit)
access : read-write


OSCCR

Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCR OSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IHOSC1N EOSCEN OSCSEL OSCF IHOSC1F

IHOSC1N : IHOSC1N
bits : 0 - 0 (1 bit)
access : read-write

EOSCEN : EOSCEN
bits : 1 - 2 (2 bit)
access : read-only

OSCSEL : OSCSEL
bits : 8 - 8 (1 bit)
access : read-write

OSCF : OSCF
bits : 9 - 9 (1 bit)
access : read-only

IHOSC1F : IHOSC1F
bits : 16 - 16 (1 bit)
access : read-only


FSYSMENA

Middle fsys Supply Stop Register A
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYSMENA FSYSMENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPMENA00 IPMENA01 IPMENA02 IPMENA03 IPMENA04 IPMENA05 IPMENA06 IPMENA07 IPMENA08 IPMENA09 IPMENA10 IPMENA11 IPMENA12 IPMENA13 IPMENA14 IPMENA15 IPMENA16 IPMENA17 IPMENA18 IPMENA19 IPMENA20 IPMENA21 IPMENA22 IPMENA23 IPMENA24 IPMENA25 IPMENA26 IPMENA27 IPMENA28 IPMENA29 IPMENA30 IPMENA31

IPMENA00 : IPMENA00
bits : 0 - 0 (1 bit)
access : read-write

IPMENA01 : IPMENA01
bits : 1 - 1 (1 bit)
access : read-write

IPMENA02 : IPMENA02
bits : 2 - 2 (1 bit)
access : read-write

IPMENA03 : IPMENA03
bits : 3 - 3 (1 bit)
access : read-write

IPMENA04 : IPMENA04
bits : 4 - 4 (1 bit)
access : read-write

IPMENA05 : IPMENA05
bits : 5 - 5 (1 bit)
access : read-write

IPMENA06 : IPMENA06
bits : 6 - 6 (1 bit)
access : read-write

IPMENA07 : IPMENA07
bits : 7 - 7 (1 bit)
access : read-write

IPMENA08 : IPMENA08
bits : 8 - 8 (1 bit)
access : read-write

IPMENA09 : IPMENA09
bits : 9 - 9 (1 bit)
access : read-write

IPMENA10 : IPMENA10
bits : 10 - 10 (1 bit)
access : read-write

IPMENA11 : IPMENA11
bits : 11 - 11 (1 bit)
access : read-write

IPMENA12 : IPMENA12
bits : 12 - 12 (1 bit)
access : read-write

IPMENA13 : IPMENA13
bits : 13 - 13 (1 bit)
access : read-write

IPMENA14 : IPMENA14
bits : 14 - 14 (1 bit)
access : read-write

IPMENA15 : IPMENA15
bits : 15 - 15 (1 bit)
access : read-write

IPMENA16 : IPMENA16
bits : 16 - 16 (1 bit)
access : read-write

IPMENA17 : IPMENA17
bits : 17 - 17 (1 bit)
access : read-write

IPMENA18 : IPMENA18
bits : 18 - 18 (1 bit)
access : read-write

IPMENA19 : IPMENA19
bits : 19 - 19 (1 bit)
access : read-write

IPMENA20 : IPMENA20
bits : 20 - 20 (1 bit)
access : read-write

IPMENA21 : IPMENA21
bits : 21 - 21 (1 bit)
access : read-write

IPMENA22 : IPMENA22
bits : 22 - 22 (1 bit)
access : read-write

IPMENA23 : IPMENA23
bits : 23 - 23 (1 bit)
access : read-write

IPMENA24 : IPMENA24
bits : 24 - 24 (1 bit)
access : read-write

IPMENA25 : IPMENA25
bits : 25 - 25 (1 bit)
access : read-write

IPMENA26 : IPMENA26
bits : 26 - 26 (1 bit)
access : read-write

IPMENA27 : IPMENA27
bits : 27 - 27 (1 bit)
access : read-write

IPMENA28 : IPMENA28
bits : 28 - 28 (1 bit)
access : read-write

IPMENA29 : IPMENA29
bits : 29 - 29 (1 bit)
access : read-write

IPMENA30 : IPMENA30
bits : 30 - 30 (1 bit)
access : read-write

IPMENA31 : IPMENA31
bits : 31 - 31 (1 bit)
access : read-write


FSYSMENB

Middle fsys Supply Stop Register A
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYSMENB FSYSMENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPMENB00 IPMENB01 IPMENB02 IPMENB03 IPMENB04 IPMENB05 IPMENB06 IPMENB07 IPMENB08 IPMENB09 IPMENB10 IPMENB11 IPMENB12 IPMENB13 IPMENB14 IPMENB15 IPMENB16 IPMENB17 IPMENB18 IPMENB19 IPMENB20 IPMENB21 IPMENB22 IPMENB23 IPMENB24 IPMENB25 IPMENB26 IPMENB27 IPMENB28 IPMENB29 IPMENB30 IPMENB31

IPMENB00 : IPMENB00
bits : 0 - 0 (1 bit)
access : read-write

IPMENB01 : IPMENB01
bits : 1 - 1 (1 bit)
access : read-write

IPMENB02 : IPMENB02
bits : 2 - 2 (1 bit)
access : read-write

IPMENB03 : IPMENB03
bits : 3 - 3 (1 bit)
access : read-write

IPMENB04 : IPMENB04
bits : 4 - 4 (1 bit)
access : read-write

IPMENB05 : IPMENB05
bits : 5 - 5 (1 bit)
access : read-write

IPMENB06 : IPMENB06
bits : 6 - 6 (1 bit)
access : read-write

IPMENB07 : IPMENB07
bits : 7 - 7 (1 bit)
access : read-write

IPMENB08 : IPMENB08
bits : 8 - 8 (1 bit)
access : read-write

IPMENB09 : IPMENB09
bits : 9 - 9 (1 bit)
access : read-write

IPMENB10 : IPMENB10
bits : 10 - 10 (1 bit)
access : read-write

IPMENB11 : IPMENB11
bits : 11 - 11 (1 bit)
access : read-write

IPMENB12 : IPMENB12
bits : 12 - 12 (1 bit)
access : read-write

IPMENB13 : IPMENB13
bits : 13 - 13 (1 bit)
access : read-write

IPMENB14 : IPMENB14
bits : 14 - 14 (1 bit)
access : read-write

IPMENB15 : IPMENB15
bits : 15 - 15 (1 bit)
access : read-write

IPMENB16 : IPMENB16
bits : 16 - 16 (1 bit)
access : read-write

IPMENB17 : IPMENB17
bits : 17 - 17 (1 bit)
access : read-write

IPMENB18 : IPMENB18
bits : 18 - 18 (1 bit)
access : read-write

IPMENB19 : IPMENB19
bits : 19 - 19 (1 bit)
access : read-write

IPMENB20 : IPMENB20
bits : 20 - 20 (1 bit)
access : read-write

IPMENB21 : IPMENB21
bits : 21 - 21 (1 bit)
access : read-write

IPMENB22 : IPMENB22
bits : 22 - 22 (1 bit)
access : read-write

IPMENB23 : IPMENB23
bits : 23 - 23 (1 bit)
access : read-write

IPMENB24 : IPMENB24
bits : 24 - 24 (1 bit)
access : read-write

IPMENB25 : IPMENB25
bits : 25 - 25 (1 bit)
access : read-write

IPMENB26 : IPMENB26
bits : 26 - 26 (1 bit)
access : read-write

IPMENB27 : IPMENB27
bits : 27 - 27 (1 bit)
access : read-write

IPMENB28 : IPMENB28
bits : 28 - 28 (1 bit)
access : read-write

IPMENB29 : IPMENB29
bits : 29 - 29 (1 bit)
access : read-write

IPMENB30 : IPMENB30
bits : 30 - 30 (1 bit)
access : read-write

IPMENB31 : IPMENB31
bits : 31 - 31 (1 bit)
access : read-write


FSYSENA

High fsys Supply Stop Register A
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYSENA FSYSENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPENA00 IPENA01 IPENA02 IPENA03 IPENA04 IPENA05 IPENA06 IPENA07 IPENA08 IPENA09

IPENA00 : IPENA00
bits : 0 - 0 (1 bit)
access : read-write

IPENA01 : IPENA01
bits : 1 - 1 (1 bit)
access : read-write

IPENA02 : IPENA02
bits : 2 - 2 (1 bit)
access : read-write

IPENA03 : IPENA03
bits : 3 - 3 (1 bit)
access : read-write

IPENA04 : IPENA04
bits : 4 - 4 (1 bit)
access : read-write

IPENA05 : IPENA05
bits : 5 - 5 (1 bit)
access : read-write

IPENA06 : IPENA06
bits : 6 - 6 (1 bit)
access : read-write

IPENA07 : IPENA07
bits : 7 - 7 (1 bit)
access : read-write

IPENA08 : IPENA08
bits : 8 - 8 (1 bit)
access : read-write

IPENA09 : IPENA09
bits : 9 - 9 (1 bit)
access : read-write


SPCLKEN

ADC TRACE Clock Supply Stop Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCLKEN SPCLKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCKEN ADCKEN0

TRCKEN : TRCKEN
bits : 0 - 0 (1 bit)
access : read-write

ADCKEN0 : ADCKEN0
bits : 16 - 16 (1 bit)
access : read-write


EXTEND2

Extend for MDMAC Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTEND2 EXTEND2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV20 REV21 REV22

REV20 : REV20
bits : 0 - 0 (1 bit)
access : read-write

REV21 : REV21
bits : 1 - 1 (1 bit)
access : read-write

REV22 : REV22
bits : 2 - 2 (1 bit)
access : read-write


SYSCR

System Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCR SYSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEAR PRCK GEARST PRCKST

GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write

PRCK : PRCK
bits : 8 - 11 (4 bit)
access : read-write

GEARST : GEARST
bits : 16 - 18 (3 bit)
access : read-only

PRCKST : PRCKST
bits : 24 - 27 (4 bit)
access : read-only


STBYCR

Standby Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STBYCR STBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY

STBY : STBY
bits : 0 - 1 (2 bit)
access : read-write



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