\n
address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected
CEC Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECEN : CECEN
bits : 0 - 0 (1 bit)
access : read-write
CEC Receive Buffer Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CECRBUF : CECRBUF
bits : 0 - 7 (8 bit)
access : read-only
CECEOM : CECEOM
bits : 8 - 8 (1 bit)
access : read-only
CECACK : CECACK
bits : 9 - 9 (1 bit)
access : read-only
CEC Receive Control Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECOTH : CECOTH
bits : 0 - 0 (1 bit)
access : read-write
CECRIHLD : CECRIHLD
bits : 1 - 1 (1 bit)
access : read-write
CECTOUT : CECTOUT
bits : 2 - 3 (2 bit)
access : read-write
CECDAT : CECDAT
bits : 4 - 6 (3 bit)
access : read-write
CECMAX : CECMAX
bits : 8 - 10 (3 bit)
access : read-write
CECMIN : CECMIN
bits : 12 - 14 (3 bit)
access : read-write
CECLNC : CECLNC
bits : 16 - 18 (3 bit)
access : read-write
CECHNC : CECHNC
bits : 20 - 21 (2 bit)
access : read-write
CECACKDIS : CECACKDIS
bits : 24 - 24 (1 bit)
access : read-write
CEC Receive Control Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECSWAV0 : CECSWAV0
bits : 0 - 2 (3 bit)
access : read-write
CECSWAV1 : CECSWAV1
bits : 4 - 6 (3 bit)
access : read-write
CECSWAV2 : CECSWAV2
bits : 8 - 10 (3 bit)
access : read-write
CECSWAV3 : CECSWAV3
bits : 12 - 14 (3 bit)
access : read-write
CEC Receive Control Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECWAVEN : CECWAVEN
bits : 0 - 0 (1 bit)
access : read-write
CECRSTAEN : CECRSTAEN
bits : 1 - 1 (1 bit)
access : read-write
CECWAV0 : CECWAV0
bits : 8 - 10 (3 bit)
access : read-write
CECWAV1 : CECWAV1
bits : 12 - 14 (3 bit)
access : read-write
CECWAV2 : CECWAV2
bits : 16 - 18 (3 bit)
access : read-write
CECWAV3 : CECWAV3
bits : 20 - 22 (3 bit)
access : read-write
CEC Transmit Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECTEN : CECTEN
bits : 0 - 0 (1 bit)
access : write-only
CECTRANS : CECTRANS
bits : 1 - 1 (1 bit)
access : read-only
CEC Transmit Buffer Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECTBUF : CECTBUF
bits : 0 - 7 (8 bit)
access : read-write
CECTEOM : CECTEOM
bits : 8 - 8 (1 bit)
access : read-write
CEC Transmit Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECFREE : CECFREE
bits : 0 - 3 (4 bit)
access : read-write
CECBRD : CECBRD
bits : 4 - 4 (1 bit)
access : read-write
CECDPRD : CECDPRD
bits : 8 - 11 (4 bit)
access : read-write
CECDTRS : CECDTRS
bits : 12 - 14 (3 bit)
access : read-write
CECSPRD : CECSPRD
bits : 16 - 18 (3 bit)
access : read-write
CECSTRS : CECSTRS
bits : 20 - 22 (3 bit)
access : read-write
CEC Receive Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CECRIEND : CECRIEND
bits : 0 - 0 (1 bit)
access : read-only
CECRISTA : CECRISTA
bits : 1 - 1 (1 bit)
access : read-only
CECRIMAX : CECRIMAX
bits : 2 - 2 (1 bit)
access : read-only
CECRIMIN : CECRIMIN
bits : 3 - 3 (1 bit)
access : read-only
CECRIACK : CECRIACK
bits : 4 - 4 (1 bit)
access : read-only
CECRIOR : CECRIOR
bits : 5 - 5 (1 bit)
access : read-only
CECRIWAV : CECRIWAV
bits : 6 - 6 (1 bit)
access : read-only
CEC Transmit Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CECTISTA : CECTISTA
bits : 0 - 0 (1 bit)
access : read-only
CECTIEND : CECTIEND
bits : 1 - 1 (1 bit)
access : read-only
CECTIAL : CECTIAL
bits : 2 - 2 (1 bit)
access : read-only
CECTIACK : CECTIACK
bits : 3 - 3 (1 bit)
access : read-only
CECTIUR : CECTIUR
bits : 4 - 4 (1 bit)
access : read-only
CEC sampling clock selection Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECCLK : CECCLK
bits : 0 - 0 (1 bit)
access : read-write
CEC Logical Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECADD : CECADD
bits : 0 - 15 (16 bit)
access : read-write
CEC Software Reset Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CECRESET : CECRESET
bits : 0 - 0 (1 bit)
access : write-only
CEC Receive Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECREN : CECREN
bits : 0 - 0 (1 bit)
access : read-write
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