\n

PL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

OD

PUP

PDN

IE

CR


DATA

Port L Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7

PL0 : PL0
bits : 0 - 0 (1 bit)
access : read-write

PL1 : PL1
bits : 1 - 1 (1 bit)
access : read-write

PL2 : PL2
bits : 2 - 2 (1 bit)
access : read-write

PL3 : PL3
bits : 3 - 3 (1 bit)
access : read-write

PL4 : PL4
bits : 4 - 4 (1 bit)
access : read-write

PL5 : PL5
bits : 5 - 5 (1 bit)
access : read-write

PL6 : PL6
bits : 6 - 6 (1 bit)
access : read-write

PL7 : PL7
bits : 7 - 7 (1 bit)
access : read-write


OD

Port L Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0OD PL1OD PL2OD PL3OD PL4OD PL5OD PL6OD PL7OD

PL0OD : PL0OD
bits : 0 - 0 (1 bit)
access : read-write

PL1OD : PL1OD
bits : 1 - 1 (1 bit)
access : read-write

PL2OD : PL2OD
bits : 2 - 2 (1 bit)
access : read-write

PL3OD : PL3OD
bits : 3 - 3 (1 bit)
access : read-write

PL4OD : PL4OD
bits : 4 - 4 (1 bit)
access : read-write

PL5OD : PL5OD
bits : 5 - 5 (1 bit)
access : read-write

PL6OD : PL6OD
bits : 6 - 6 (1 bit)
access : read-write

PL7OD : PL7OD
bits : 7 - 7 (1 bit)
access : read-write


PUP

Port L Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0UP PL1UP PL2UP PL3UP PL4UP PL5UP PL6UP PL7UP

PL0UP : PL0UP
bits : 0 - 0 (1 bit)
access : read-write

PL1UP : PL1UP
bits : 1 - 1 (1 bit)
access : read-write

PL2UP : PL2UP
bits : 2 - 2 (1 bit)
access : read-write

PL3UP : PL3UP
bits : 3 - 3 (1 bit)
access : read-write

PL4UP : PL4UP
bits : 4 - 4 (1 bit)
access : read-write

PL5UP : PL5UP
bits : 5 - 5 (1 bit)
access : read-write

PL6UP : PL6UP
bits : 6 - 6 (1 bit)
access : read-write

PL7UP : PL7UP
bits : 7 - 7 (1 bit)
access : read-write


PDN

Port L Pull-down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDN PDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0DN PL1DN PL2DN PL3DN PL4DN PL5DN PL6DN PL7DN

PL0DN : PL0DN
bits : 0 - 0 (1 bit)
access : read-write

PL1DN : PL1DN
bits : 1 - 1 (1 bit)
access : read-write

PL2DN : PL2DN
bits : 2 - 2 (1 bit)
access : read-write

PL3DN : PL3DN
bits : 3 - 3 (1 bit)
access : read-write

PL4DN : PL4DN
bits : 4 - 4 (1 bit)
access : read-write

PL5DN : PL5DN
bits : 5 - 5 (1 bit)
access : read-write

PL6DN : PL6DN
bits : 6 - 6 (1 bit)
access : read-write

PL7DN : PL7DN
bits : 7 - 7 (1 bit)
access : read-write


IE

Port L Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0IE PL1IE PL2IE PL3IE PL4IE PL5IE PL6IE PL7IE

PL0IE : PL0IE
bits : 0 - 0 (1 bit)
access : read-write

PL1IE : PL1IE
bits : 1 - 1 (1 bit)
access : read-write

PL2IE : PL2IE
bits : 2 - 2 (1 bit)
access : read-write

PL3IE : PL3IE
bits : 3 - 3 (1 bit)
access : read-write

PL4IE : PL4IE
bits : 4 - 4 (1 bit)
access : read-write

PL5IE : PL5IE
bits : 5 - 5 (1 bit)
access : read-write

PL6IE : PL6IE
bits : 6 - 6 (1 bit)
access : read-write

PL7IE : PL7IE
bits : 7 - 7 (1 bit)
access : read-write


CR

Port L Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0C PL1C PL2C PL3C PL4C PL5C PL6C PL7C

PL0C : PL0C
bits : 0 - 0 (1 bit)
access : read-write

PL1C : PL1C
bits : 1 - 1 (1 bit)
access : read-write

PL2C : PL2C
bits : 2 - 2 (1 bit)
access : read-write

PL3C : PL3C
bits : 3 - 3 (1 bit)
access : read-write

PL4C : PL4C
bits : 4 - 4 (1 bit)
access : read-write

PL5C : PL5C
bits : 5 - 5 (1 bit)
access : read-write

PL6C : PL6C
bits : 6 - 6 (1 bit)
access : read-write

PL7C : PL7C
bits : 7 - 7 (1 bit)
access : read-write



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