\n

EN0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TNCR

MCMP

RATE

STS

INPCR

SMPDLY

INPMON

CLKCR

INTCR

INTF

RELOAD

INT

CNT


TNCR

ENC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNCR TNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDEV ZEACT ENRUN ZEN ZESEL ENCLR SFTCAP TRGCAPMD P3EN MODE SDTEN DECMD MCMPMD TOVMD UDMD CMPSEL

ENDEV : ENDEV
bits : 0 - 2 (3 bit)
access : read-write

ZEACT : ZEACT
bits : 5 - 5 (1 bit)
access : read-write

ENRUN : ENRUN
bits : 6 - 6 (1 bit)
access : read-write

ZEN : ZEN
bits : 7 - 7 (1 bit)
access : read-write

ZESEL : ZESEL
bits : 8 - 9 (2 bit)
access : read-write

ENCLR : ENCLR
bits : 10 - 10 (1 bit)
access : write-only

SFTCAP : SFTCAP
bits : 11 - 11 (1 bit)
access : write-only

TRGCAPMD : TRGCAPMD
bits : 12 - 12 (1 bit)
access : read-write

P3EN : P3EN
bits : 16 - 16 (1 bit)
access : read-write

MODE : MODE
bits : 17 - 19 (3 bit)
access : read-write

SDTEN : SDTEN
bits : 21 - 21 (1 bit)
access : read-write

DECMD : DECMD
bits : 22 - 23 (2 bit)
access : read-write

MCMPMD : MCMPMD
bits : 24 - 24 (1 bit)
access : read-write

TOVMD : TOVMD
bits : 25 - 25 (1 bit)
access : read-write

UDMD : UDMD
bits : 26 - 27 (2 bit)
access : read-write

CMPSEL : CMPSEL
bits : 28 - 28 (1 bit)
access : read-write


MCMP

ENC MCMP Compare Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCMP MCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCMP

MCMP : MCMP
bits : 0 - 31 (32 bit)
access : read-write


RATE

ENC Phase Count Rate Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RATE RATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATE

RATE : RATE
bits : 0 - 15 (16 bit)
access : read-write


STS

ENC Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STS STS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INERR PDERR SKPDT ZDET UD REVERR

INERR : INERR
bits : 0 - 0 (1 bit)
access : read-only

PDERR : PDERR
bits : 1 - 1 (1 bit)
access : read-only

SKPDT : SKPDT
bits : 2 - 2 (1 bit)
access : read-only

ZDET : ZDET
bits : 12 - 12 (1 bit)
access : read-only

UD : UD
bits : 13 - 13 (1 bit)
access : read-only

REVERR : REVERR
bits : 14 - 14 (1 bit)
access : read-only


INPCR

ENC Input Process Cntrol Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INPCR INPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCSPLEN SYNCSPLMD SYNCNCZEN PDSTT PDSTP NCT

SYNCSPLEN : SYNCSPLEN
bits : 0 - 0 (1 bit)
access : read-write

SYNCSPLMD : SYNCSPLMD
bits : 1 - 1 (1 bit)
access : read-write

SYNCNCZEN : SYNCNCZEN
bits : 2 - 2 (1 bit)
access : read-write

PDSTT : PDSTT
bits : 6 - 6 (1 bit)
access : write-only

PDSTP : PDSTP
bits : 7 - 7 (1 bit)
access : write-only

NCT : NCT
bits : 8 - 14 (7 bit)
access : read-write


SMPDLY

ENC Sample Delay Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPDLY SMPDLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPDLY

SMPDLY : SMPDLY
bits : 0 - 7 (8 bit)
access : read-write


INPMON

ENC Input Moniter Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INPMON INPMON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPLMONA SPLMONB SPLMONZ DETMONA DETMONB DETMONZ

SPLMONA : SPLMONA
bits : 0 - 0 (1 bit)
access : read-only

SPLMONB : SPLMONB
bits : 1 - 1 (1 bit)
access : read-only

SPLMONZ : SPLMONZ
bits : 2 - 2 (1 bit)
access : read-only

DETMONA : DETMONA
bits : 4 - 4 (1 bit)
access : read-only

DETMONB : DETMONB
bits : 5 - 5 (1 bit)
access : read-only

DETMONZ : DETMONZ
bits : 6 - 6 (1 bit)
access : read-only


CLKCR

ENC Sample Clock Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCR CLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPLCKS

SPLCKS : SPLCKS
bits : 0 - 1 (2 bit)
access : read-write


INTCR

ENC Interrupt Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCR INTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPLSIE CAPIE ERRIE CMPIE RLDIE MCMPIE

TPLSIE : TPLSIE
bits : 0 - 0 (1 bit)
access : read-write

CAPIE : CAPIE
bits : 1 - 1 (1 bit)
access : read-write

ERRIE : ERRIE
bits : 2 - 2 (1 bit)
access : read-write

CMPIE : CMPIE
bits : 3 - 3 (1 bit)
access : read-write

RLDIE : RLDIE
bits : 4 - 4 (1 bit)
access : read-write

MCMPIE : MCMPIE
bits : 5 - 5 (1 bit)
access : read-write


INTF

ENC Interrupt Event Flag Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPLSF CAPF ERRF INTCPF RLDCPF MCMPF

TPLSF : TPLSF
bits : 0 - 0 (1 bit)
access : read-only

CAPF : CAPF
bits : 1 - 1 (1 bit)
access : read-only

ERRF : ERRF
bits : 2 - 2 (1 bit)
access : read-only

INTCPF : INTCPF
bits : 3 - 3 (1 bit)
access : read-only

RLDCPF : RLDCPF
bits : 4 - 4 (1 bit)
access : read-only

MCMPF : MCMPF
bits : 5 - 5 (1 bit)
access : read-only


RELOAD

ENC Reload Compare Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RELOAD RELOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD

RELOAD : RELOAD
bits : 0 - 31 (32 bit)
access : read-write


INT

ENC INT Compare Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT

INT : INT
bits : 0 - 31 (32 bit)
access : read-write


CNT

ENC Counter_Capture Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 31 (32 bit)
access : read-only



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