\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected
DMA Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MASTER_ENABLE : MASTER_ENABLE
bits : 0 - 0 (1 bit)
access : read-only
DMA Channel Software Request Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNL_SW_REQUEST : CHNL_SW_REQUEST
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Useburst Set Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_USEBURST_SET : CHNL_USEBURST_SET
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel Useburst Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNL_USEBURST_CLR : CHNL_USEBURST_CLR
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Request Mask Set Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_REQ_MASK_SET : CHNL_REQ_MASK_SET
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel Request Mask Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNL_REQ_MASK_CLR : CHNL_REQ_MASK_CLR
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Enable Set Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE_SET : CHNL_ENABLE_SET
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel Enable Clear Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE_CLR : CHNL_ENABLE_CLR
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Primary-Alternate Set Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_PRI_ALT_SET : CHNL_PRI_ALT_SET
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel Primary-Alternate Clear Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNL_PRI_ALT_CLR : CHNL_PRI_ALT_CLR
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Priority Set Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_PRIORITY_SET : CHNL_PRIORITY_SET
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel Priority Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNL_PRIORITY_CLR : CHNL_PRIORITY_CLR
bits : 0 - 31 (32 bit)
access : write-only
DMA Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MASTER_ENABLE : MASTER_ENABLE
bits : 0 - 0 (1 bit)
access : write-only
DMA Bus Error Clear Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR_CLR : ERR_CLR
bits : 0 - 0 (1 bit)
access : read-write
DMA Control Data Base Pointer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_BASE_PTR : CTRL_BASE_PTR
bits : 10 - 31 (22 bit)
access : read-write
DMA Channel Alternate Control Data Base Pointer Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ALT_CTRL_BASE_PTR : ALT_CTRL_BASE_PTR
bits : 0 - 31 (32 bit)
access : read-only
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